From 4269c43e64f348cb713c0ac7140fd5194eb06b0b Mon Sep 17 00:00:00 2001
From: Ankit Sharma <quic_anshar@quicinc.com>
Date: Mon, 4 Nov 2024 13:50:54 +0530
Subject: [PATCH] ARM: dts: msm: tuna: Update capacity property

Update "capacity-dmips-mhz" for tuna. It is used to build Energy Model
which in turn is used by EAS to take placement decisions.

Change-Id: If4c0886b8a683e63f32f700f53968a1e2dbd1e42
Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
---
 qcom/tuna.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi
index e0d24717..fb688352 100644
--- a/qcom/tuna.dtsi
+++ b/qcom/tuna.dtsi
@@ -154,7 +154,7 @@
 			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_2>;
-			capacity-dmips-mhz = <1035>;
+			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <121>;
 			L2_2: l2-cache {
 			      compatible = "cache";
@@ -175,7 +175,7 @@
 			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_3>;
-			capacity-dmips-mhz = <1035>;
+			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <121>;
 			L2_3: l2-cache {
 			      compatible = "cache";
@@ -196,7 +196,7 @@
 			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_4>;
-			capacity-dmips-mhz = <1035>;
+			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <121>;
 			L2_4: l2-cache {
 			      compatible = "cache";
@@ -217,7 +217,7 @@
 			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_5>;
-			capacity-dmips-mhz = <1035>;
+			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <121>;
 			L2_5: l2-cache {
 			      compatible = "cache";
@@ -238,7 +238,7 @@
 			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_6>;
-			capacity-dmips-mhz = <1035>;
+			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <121>;
 			L2_6: l2-cache {
 			      compatible = "cache";
@@ -259,7 +259,7 @@
 			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_7>;
-			capacity-dmips-mhz = <1178>;
+			capacity-dmips-mhz = <1157>;
 			dynamic-power-coefficient = <295>;
 			L2_7: l2-cache {
 			      compatible = "cache";