From 95a4f259ef298c6f9d513230d8fa5fe4e81145f5 Mon Sep 17 00:00:00 2001
From: Manish Pandey <quic_mapa@quicinc.com>
Date: Fri, 4 Oct 2024 15:24:19 +0530
Subject: [PATCH] ARM: dts: msm: Add SDCC support for tuna

Add SD Card support for tuna atp, cdp, mtp and qrd platform.

Change-Id: I2450eeb4e3b525b30082495d79a6d896e290a891
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
---
 qcom/tuna-cdp.dtsi | 27 +++++++++++++++++++++++++++
 qcom/tuna-mtp.dtsi | 28 ++++++++++++++++++++++++++++
 qcom/tuna-qrd.dtsi | 26 ++++++++++++++++++++++++++
 3 files changed, 81 insertions(+)

diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi
index 44461ef5..6b85652a 100644
--- a/qcom/tuna-cdp.dtsi
+++ b/qcom/tuna-cdp.dtsi
@@ -3,6 +3,9 @@
  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/qcom,gcc-sun.h>
+
 &qupv3_se4_i2c {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -83,3 +86,27 @@
 
 	status = "ok";
 };
+
+&sdhc_2 {
+	vdd-supply = <&L13B>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 976310>;
+
+	vdd-io-supply = <&L23B>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 5830>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+	resets = <&gcc GCC_SDCC2_BCR>;
+	reset-names = "core_reset";
+
+	qcom,uses_level_shifter;
+
+	status = "ok";
+};
+
diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi
index 12fe6b41..6b85652a 100644
--- a/qcom/tuna-mtp.dtsi
+++ b/qcom/tuna-mtp.dtsi
@@ -2,6 +2,10 @@
 /*
  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/qcom,gcc-sun.h>
+
 &qupv3_se4_i2c {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -82,3 +86,27 @@
 
 	status = "ok";
 };
+
+&sdhc_2 {
+	vdd-supply = <&L13B>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 976310>;
+
+	vdd-io-supply = <&L23B>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 5830>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+	resets = <&gcc GCC_SDCC2_BCR>;
+	reset-names = "core_reset";
+
+	qcom,uses_level_shifter;
+
+	status = "ok";
+};
+
diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi
index f307bb6f..9f3dcf28 100644
--- a/qcom/tuna-qrd.dtsi
+++ b/qcom/tuna-qrd.dtsi
@@ -2,6 +2,8 @@
 /*
  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/qcom,gcc-sun.h>
 
 &qupv3_se4_spi {
 	#address-cells = <1>;
@@ -86,3 +88,27 @@
 
 	status = "ok";
 };
+
+&sdhc_2 {
+	vdd-supply = <&L13B>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 976310>;
+
+	vdd-io-supply = <&L23B>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 5830>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+	resets = <&gcc GCC_SDCC2_BCR>;
+	reset-names = "core_reset";
+
+	qcom,uses_level_shifter;
+
+	status = "ok";
+};
+