From 956a4269fcd748bfd69cccb4c2a25b6e75006381 Mon Sep 17 00:00:00 2001
From: Linux Image Build Automation <quic_ibautomat@quicinc.com>
Date: Wed, 17 Jul 2024 01:30:18 -0700
Subject: [PATCH] Revert "ARM: dts: msm: Update Sun V2 GPU frequencies"

This reverts commit 154f54c2c999638fe6852cb72ec779111d59ce42.

Change-Id: I1467766328bdd388756d9a2f953b6ad08d72c8a7
Signed-off-by: Linux Image Build Automation <quic_ibautomat@quicinc.com>
---
 gpu/sun-v2-gpu-pwrlevels.dtsi | 72 ++++++++++++++---------------------
 1 file changed, 29 insertions(+), 43 deletions(-)

diff --git a/gpu/sun-v2-gpu-pwrlevels.dtsi b/gpu/sun-v2-gpu-pwrlevels.dtsi
index 3418c791..7a70ac8d 100644
--- a/gpu/sun-v2-gpu-pwrlevels.dtsi
+++ b/gpu/sun-v2-gpu-pwrlevels.dtsi
@@ -4,7 +4,6 @@
  */
 
 /* ACD Control register values */
-#define ACD_LEVEL_TURBO_L4    0x88295ffd
 #define ACD_LEVEL_TURBO_L3    0x882a5ffd
 #define ACD_LEVEL_TURBO_L1    0x882a5ffd
 #define ACD_LEVEL_NOM_L1      0x882b5ffd
@@ -355,26 +354,13 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			qcom,initial-pwrlevel = <14>;
+			qcom,initial-pwrlevel = <13>;
 			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
 
-			/* TURBO_L4 */
+			/* TURBO_L3 */
 			qcom,gpu-pwrlevel@0 {
 				reg = <0>;
-				qcom,gpu-freq = <1200000000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
-
-				qcom,bus-freq = <11>;
-				qcom,bus-min = <11>;
-				qcom,bus-max = <11>;
-
-				qcom,acd-level = <ACD_LEVEL_TURBO_L4>;
-			};
-
-			/* TURBO_L3 */
-			qcom,gpu-pwrlevel@1 {
-				reg = <1>;
-				qcom,gpu-freq = <1100000000>;
+				qcom,gpu-freq = <1150000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
 
 				qcom,bus-freq = <11>;
@@ -385,8 +371,8 @@
 			};
 
 			/* TURBO_L1 */
-			qcom,gpu-pwrlevel@2 {
-				reg = <2>;
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
 				qcom,gpu-freq = <1050000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 
@@ -398,8 +384,8 @@
 			};
 
 			/* NOM_L1 */
-			qcom,gpu-pwrlevel@3 {
-				reg = <3>;
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
 				qcom,gpu-freq = <967000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 
@@ -411,8 +397,8 @@
 			};
 
 			/* NOM */
-			qcom,gpu-pwrlevel@4 {
-				reg = <4>;
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
 				qcom,gpu-freq = <900000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
 
@@ -424,8 +410,8 @@
 			};
 
 			/* SVS_L2 */
-			qcom,gpu-pwrlevel@5 {
-				reg = <5>;
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
 				qcom,gpu-freq = <832000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 
@@ -437,8 +423,8 @@
 			};
 
 			/* SVS_L1 */
-			qcom,gpu-pwrlevel@6 {
-				reg = <6>;
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
 				qcom,gpu-freq = <734000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 
@@ -450,8 +436,8 @@
 			};
 
 			/* SVS_L0 */
-			qcom,gpu-pwrlevel@7 {
-				reg = <7>;
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
 				qcom,gpu-freq = <660000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
 
@@ -463,8 +449,8 @@
 			};
 
 			/* SVS */
-			qcom,gpu-pwrlevel@8 {
-				reg = <8>;
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
 				qcom,gpu-freq = <607000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
 
@@ -476,8 +462,8 @@
 			};
 
 			/* Low_SVS_L1 */
-			qcom,gpu-pwrlevel@9 {
-				reg = <9>;
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
 				qcom,gpu-freq = <525000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
 
@@ -489,8 +475,8 @@
 			};
 
 			/* Low_SVS */
-			qcom,gpu-pwrlevel@10 {
-				reg = <10>;
+			qcom,gpu-pwrlevel@9 {
+				reg = <9>;
 				qcom,gpu-freq = <443000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 
@@ -502,8 +488,8 @@
 			};
 
 			/* Low_SVS_D0 */
-			qcom,gpu-pwrlevel@11 {
-				reg = <11>;
+			qcom,gpu-pwrlevel@10 {
+				reg = <10>;
 				qcom,gpu-freq = <389000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
 
@@ -515,8 +501,8 @@
 			};
 
 			/* Low_SVS_D1 */
-			qcom,gpu-pwrlevel@12 {
-				reg = <12>;
+			qcom,gpu-pwrlevel@11 {
+				reg = <11>;
 				qcom,gpu-freq = <342000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
 
@@ -528,8 +514,8 @@
 			};
 
 			/* Low_SVS_D2 */
-			qcom,gpu-pwrlevel@13 {
-				reg = <13>;
+			qcom,gpu-pwrlevel@12 {
+				reg = <12>;
 				qcom,gpu-freq = <222000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
 
@@ -541,8 +527,8 @@
 			};
 
 			/* Low_SVS_D3 */
-			qcom,gpu-pwrlevel@14 {
-				reg = <14>;
+			qcom,gpu-pwrlevel@13 {
+				reg = <13>;
 				qcom,gpu-freq = <160000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;