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Merge "dt-bindings: clock: qcom: add VIDEO/EVA clock controller bindings on tuna"

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This commit is contained in:
qctecmdr
2024-06-16 23:19:54 -07:00
committed by Gerrit - the friendly Code Review server
parent d8f258e96f 2bf1b02b65
commit 94873196df
3 changed files with 42 additions and 13 deletions
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7
bindings/clock/qcom,evacc-sun.yaml
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@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,evacc-sun.yaml# $id: http://devicetree.org/schemas/clock/qcom,evacc-sun.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Eva Clock Controller Binding for SUN title: Qualcomm Technologies, Inc. Eva Clock Controller for SUN
maintainers: maintainers:
- Xubin Bai <quic_xubibai@quicinc.com> - Xubin Bai <quic_xubibai@quicinc.com>
@@ -14,10 +14,13 @@ description: |
See also: See also:
- dt-bindings/clock/qcom,evacc-sun.h - dt-bindings/clock/qcom,evacc-sun.h
- dt-bindings/clock/qcom,evacc-tuna.h
properties: properties:
compatible: compatible:
const: qcom,sun-evacc enum:
- qcom,sun-evacc
- qcom,tuna-evacc
clocks: clocks:
items: items:

2
bindings/clock/qcom,videocc.yaml
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@@ -22,6 +22,7 @@ description: |
dt-bindings/clock/qcom,videocc-pineapple.h dt-bindings/clock/qcom,videocc-pineapple.h
dt-bindings/clock/qcom,videocc-sun.h dt-bindings/clock/qcom,videocc-sun.h
dt-bindings/clock/qcom,videocc-parrot.h dt-bindings/clock/qcom,videocc-parrot.h
dt-bindings/clock/qcom,videocc-tuna.h
properties: properties:
compatible: compatible:
@@ -36,6 +37,7 @@ properties:
- qcom,sun-videocc - qcom,sun-videocc
- qcom,sun-videocc-v2 - qcom,sun-videocc-v2
- qcom,parrot-videocc - qcom,parrot-videocc
- qcom,tuna-videocc
clocks: clocks:
items: items:

46
qcom/tuna.dtsi
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@@ -549,8 +549,25 @@
}; };
gcc: clock-controller@100000 { gcc: clock-controller@100000 {
compatible = "qcom,dummycc"; compatible = "qcom,tuna-gcc", "syscon";
clock-output-names = "gcc_clocks"; reg = <0x100000 0x1f4200>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&pcie_0_pipe_clk>,
<&sleep_clk>,
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo",
"pcie_0_pipe_clk",
"sleep_clk",
"ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk",
"ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
@@ -562,9 +579,10 @@
#reset-cells = <1>; #reset-cells = <1>;
}; };
tcsrcc: clock-controller@f100000 { tcsrcc: clock-controller@1fbf000 {
compatible = "qcom,dummycc"; compatible = "qcom,tuna-tcsrcc", "syscon";
clock-output-names = "tcsrcc_clocks"; reg = <0x1fbf000 0x14>;
reg-name = "cc_base";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
@@ -631,32 +649,38 @@
}; };
&gcc_pcie_0_gdsc { &gcc_pcie_0_gdsc {
compatible = "regulator-fixed"; compatible = "qcom,gdsc";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_pcie_0_phy_gdsc { &gcc_pcie_0_phy_gdsc {
compatible = "regulator-fixed"; compatible = "qcom,gdsc";
parent-supply = <&VDD_MX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_ufs_mem_phy_gdsc { &gcc_ufs_mem_phy_gdsc {
compatible = "regulator-fixed"; compatible = "qcom,gdsc";
parent-supply = <&VDD_MX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_ufs_phy_gdsc { &gcc_ufs_phy_gdsc {
compatible = "regulator-fixed"; compatible = "qcom,gdsc";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_usb30_prim_gdsc { &gcc_usb30_prim_gdsc {
compatible = "regulator-fixed"; compatible = "qcom,gdsc";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_usb3_phy_gdsc { &gcc_usb3_phy_gdsc {
compatible = "regulator-fixed"; compatible = "qcom,gdsc";
parent-supply = <&VDD_MX_LEVEL>;
status = "ok"; status = "ok";
}; };