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ARM: dts: msm: tuna: Update capacity property

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Update "capacity-dmips-mhz" for tuna. It is used to build Energy Model
which in turn is used by EAS to take placement decisions.

Change-Id: I7e0ad3f42d39303e044b6fbc7cfd3f76492d09de
Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
This commit is contained in:
Ankit Sharma
2024-10-08 12:23:50 +05:30
parent e203547e9a
commit 90b3ccd884
1 changed files with 6 additions and 6 deletions
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qcom/tuna.dtsi
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@@ -137,7 +137,7 @@
power-domain-names = "psci"; power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>; dynamic-power-coefficient = <121>;
L2_2: l2-cache { L2_2: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -156,7 +156,7 @@
power-domain-names = "psci"; power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>; dynamic-power-coefficient = <121>;
L2_3: l2-cache { L2_3: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -175,7 +175,7 @@
power-domain-names = "psci"; power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_4>; next-level-cache = <&L2_4>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>; dynamic-power-coefficient = <121>;
L2_4: l2-cache { L2_4: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -194,7 +194,7 @@
power-domain-names = "psci"; power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_5>; next-level-cache = <&L2_5>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>; dynamic-power-coefficient = <121>;
L2_5: l2-cache { L2_5: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -213,7 +213,7 @@
power-domain-names = "psci"; power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_6>; next-level-cache = <&L2_6>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>; dynamic-power-coefficient = <121>;
L2_6: l2-cache { L2_6: l2-cache {
compatible = "cache"; compatible = "cache";
@@ -232,7 +232,7 @@
power-domain-names = "psci"; power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_7>; next-level-cache = <&L2_7>;
capacity-dmips-mhz = <1300>; capacity-dmips-mhz = <1178>;
dynamic-power-coefficient = <295>; dynamic-power-coefficient = <295>;
L2_7: l2-cache { L2_7: l2-cache {
compatible = "cache"; compatible = "cache";