diff --git a/bindings/arm/msm/sys-pm-violators.yaml b/bindings/arm/msm/sys-pm-violators.yaml index 3883054a..5fda0cf8 100644 --- a/bindings/arm/msm/sys-pm-violators.yaml +++ b/bindings/arm/msm/sys-pm-violators.yaml @@ -28,6 +28,7 @@ properties: - qcom,sys-pm-sun - qcom,sys-pm-tuna - qcom,sys-pm-kera + - qcom,sys-pm-sdxkova reg: maxItems: 1 @@ -55,6 +56,8 @@ allOf: - qcom,sys-pm-pineapple - qcom,sys-pm-parrot - qcom,sys-pm-ravelin + - qcom,sys-pm-sdxkova + then: properties: reg: diff --git a/bindings/soc/qcom/qcom,pcie-pdc.yaml b/bindings/soc/qcom/qcom,pcie-pdc.yaml index 62a9f3fe..5e4ec249 100644 --- a/bindings/soc/qcom/qcom,pcie-pdc.yaml +++ b/bindings/soc/qcom/qcom,pcie-pdc.yaml @@ -24,6 +24,7 @@ properties: - qcom,tuna-pcie-pdc - qcom,kera-pcie-pdc - qcom,pcie-pdc + - qcom,sdxkova-pcie-pdc reg: maxItems: 1 diff --git a/qcom/kera-coresight.dtsi b/qcom/kera-coresight.dtsi index 4bc74ecd..20e98fc3 100644 --- a/qcom/kera-coresight.dtsi +++ b/qcom/kera-coresight.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &soc { @@ -2844,6 +2844,7 @@ reg-names = "tpdm-base"; coresight-name = "coresight-tpdm-qm"; + status = "disabled"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; diff --git a/qcom/kera-regulators.dtsi b/qcom/kera-regulators.dtsi index aa1caf42..fdd2d473 100644 --- a/qcom/kera-regulators.dtsi +++ b/qcom/kera-regulators.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -289,7 +289,7 @@ qcom,resource-name = "ldob11"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; qcom,mode-threshold-currents = <0 30000>; @@ -299,7 +299,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; qcom,init-voltage = <1800000>; - qcom,init-mode = ; + qcom,init-mode = ; regulator-always-on; }; }; diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 343aecd6..fe33cdd8 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -22,6 +22,14 @@ status = "disabled"; }; +&disp_crm { + status = "disabled"; +}; + +&pcie_crm { + status = "disabled"; +}; + &soc { usb_emuphy: phy@a784000 { compatible = "qcom,usb-emu-phy"; diff --git a/qcom/kera-thermal.dtsi b/qcom/kera-thermal.dtsi index 036869cd..702adca7 100644 --- a/qcom/kera-thermal.dtsi +++ b/qcom/kera-thermal.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -957,7 +957,7 @@ gpuss-0 { - polling-delay-passive = <0>; + polling-delay-passive = <10>; polling-delay = <0>; thermal-sensors = <&tsens1 8>; @@ -996,7 +996,7 @@ }; gpuss-1 { - polling-delay-passive = <0>; + polling-delay-passive = <10>; polling-delay = <0>; thermal-sensors = <&tsens1 9>; @@ -1156,7 +1156,7 @@ }; mdmss-0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens2 1>; @@ -1215,7 +1215,7 @@ }; mdmss-1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens2 2>; @@ -1274,7 +1274,7 @@ }; mdmss-2 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens2 3>; @@ -1333,7 +1333,7 @@ }; mdmss-3 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens2 4>; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index a037687a..9c0f2fe9 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -19,6 +19,8 @@ #include #include #include +#include +#include / { model = "Qualcomm Technologies, Inc. Kera"; @@ -82,7 +84,6 @@ offline-sizes = <0x2 0xc0000000 0x1 0x0>; granule = <512>; qcom,qmp = <&aoss_qmp>; - status = "disabled"; }; firmware: firmware { @@ -683,6 +684,42 @@ }; }; + disp_crm: crm@af21000 { + label = "disp_crm"; + compatible = "qcom,disp-crm-v2"; + reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27400 0x400>, + <0xaf27800 0x2000>, <0xaf29800 0x700>, <0xaf29f00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; + interrupts = , + , + , + , + , + ; + interrupt-names = "disp_crm_drv0", + "disp_crm_drv1", + "disp_crm_drv2", + "disp_crm_drv3", + "disp_crm_drv4", + "disp_crm_drv5"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + qcom,hw-drv-ids = <0 1 2 3 4 5>; + qcom,sw-drv-ids = <0 1 2 3 4 5>; + }; + + pcie_crm: crm@1d01000 { + label = "pcie_crm"; + compatible = "qcom,pcie-crm-v2"; + reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03400 0x400>, + <0x1d03800 0x2000>, <0x1d05800 0x700>, <0x1d05f00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; + interrupts = ; + interrupt-names = "pcie_crm_drv0"; + clocks = <&pcie_0_pipe_clk>; + qcom,hw-drv-ids = <0 1>; + qcom,sw-drv-ids = <0>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,kera-pdc", "qcom,pdc"; reg = <0xb220000 0x10000>, <0x174000f0 0x64>; @@ -1066,6 +1103,10 @@ }; }; + qcom,glink { + compatible = "qcom,glink"; + }; + sys-pm-vx@c320000 { compatible = "qcom,sys-pm-violators", "qcom,sys-pm-kera"; reg = <0xc320000 0x400>; @@ -1260,6 +1301,12 @@ "llcc_broadcast_or_base", "llcc_broadcast_and_base"; interrupts = ; cap-based-alloc-and-pwr-collapse; + + llcc_perfmon { + compatible = "qcom,llcc-perfmon"; + clocks = <&aoss_qmp QDSS_CLK>; + clock-names = "qdss_clk"; + }; }; gic-interrupt-router { @@ -2070,6 +2117,12 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + gh-rm-booster { + compatible = "qcom,gh-rm-booster"; + qcom,rm-vmid = <255>; + qcom,rm-affinity-default = <0>; + }; + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring { size = <0x4000>; gunyah-label = <0x11>; @@ -2293,6 +2346,90 @@ compatible = "qcom,cpufreq-stats-v2"; }; + qcom_mpam: qcom,mpam { + compatible = "qcom,mpam"; + }; + + cpu_mpam: qcom,cpu_mpam { + compatible = "qcom,cpu-mpam"; + + L3 { + qcom,msc-id = <0>; + qcom,msc-name = "L3"; + }; + }; + + noc_bw_mpam: qcom,noc_bw_mpam { + compatible = "qcom,platform-mpam"; + reg = <0x17D2E800 0x400>; + reg-names = "mon-base"; + qcom,msc-id = <3>; + qcom,msc-name = "noc_bw"; + qcom,gears = "low", "medium", "high", "veryhigh"; + qcom,gear-id = <1>, <2>, <3>, <4>; + + cpu { + qcom,client-id = <0x1>; + qcom,client-name = "cpu"; + }; + + gpu { + qcom,client-id = <0x10>; + qcom,client-name = "gpu"; + }; + + nsp { + qcom,client-id = <0x100>; + qcom,client-name = "nsp"; + }; + }; + + qcom-mpam-msc { + compatible = "qcom,mpam-msc"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom-slc-mpam@17D2EC00 { + compatible = "qcom,slc-mpam"; + reg = <0x17D2EC00 0x400>; + reg-names = "mon-base"; + qcom,msc-id = <2>; + qcom,msc-name = "slc"; + qcom,dev-index = <0>; + qcom,num-read-miss-cfg = <2>; + qcom,num-cap-cfg = <5>; + qcom,slc-clients = "APPS_CLIENT", "GPU_CLIENT"; + }; + }; + + qcom_slc_mpam: qcom,slc_mpam { + compatible = "qcom,mpam-slc"; + qcom,msc-name = "slc"; + + apps { + qcom,client-id = <0>; + qcom,client-name = "apps"; + + part-id0 { + qcom,part-id = <0>; + }; + + part-id1 { + qcom,part-id = <1>; + }; + + part-id2 { + qcom,part-id = <2>; + }; + }; + + gpu { + qcom,client-id = <1>; + qcom,client-name = "gpu"; + }; + }; + spmi_bus: spmi0_bus: qcom,spmi@c42d000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc42d000 0x4000>, diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index 5130ff86..45e8626f 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -276,6 +276,23 @@ compatible = "qcom,lpm-cluster-dev"; power-domains = <&CLUSTER_PD>; }; + + pcie_crm: crm@501000 { + label = "pcie_crm"; + compatible = "qcom,pcie-crm"; + reg = <0x0 0x501000 0x0 0x3000>, <0x0 0x504800 0x0 0x800>, <0x0 0x505000 0x0 0x2000>, <0x0 0x504000 0x0 0x800>; + reg-names = "base", "crm_b", "crm_c", "crm_v"; + interrupts = ; + interrupt-names = "pcie_crm"; + clocks = <&pcie_pipe_clk>; + qcom,hw-drv-ids = <0>; + qcom,sw-drv-ids = <0>; + }; + + pcie_pdc: pdc@b2b0000 { + compatible = "qcom,sdxkova-pcie-pdc", "qcom,pcie-pdc"; + reg = <0x0 0xb2b0000 0x0 0x30000>; + }; }; firmware: firmware { }; diff --git a/qcom/tuna-regulators.dtsi b/qcom/tuna-regulators.dtsi index 8071f35e..157ecf02 100644 --- a/qcom/tuna-regulators.dtsi +++ b/qcom/tuna-regulators.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -963,7 +963,7 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; qcom,init-voltage = <1200000>; - qcom,init-mode = ; + qcom,init-mode = ; regulator-always-on; }; }; diff --git a/qcom/tuna-thermal.dtsi b/qcom/tuna-thermal.dtsi index f555783e..1a844d48 100644 --- a/qcom/tuna-thermal.dtsi +++ b/qcom/tuna-thermal.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1211,7 +1211,7 @@ }; gpu-0 { - polling-delay-passive = <0>; + polling-delay-passive = <10>; polling-delay = <0>; thermal-sensors = <&tsens2 5>; @@ -1250,7 +1250,7 @@ }; gpu-1 { - polling-delay-passive = <0>; + polling-delay-passive = <10>; polling-delay = <0>; thermal-sensors = <&tsens2 6>; @@ -1289,7 +1289,7 @@ }; gpu-2 { - polling-delay-passive = <0>; + polling-delay-passive = <10>; polling-delay = <0>; thermal-sensors = <&tsens2 7>; @@ -1328,7 +1328,7 @@ }; gpu-3 { - polling-delay-passive = <0>; + polling-delay-passive = <10>; polling-delay = <0>; thermal-sensors = <&tsens2 8>; @@ -1367,7 +1367,7 @@ }; gpu-4 { - polling-delay-passive = <0>; + polling-delay-passive = <10>; polling-delay = <0>; thermal-sensors = <&tsens2 9>; @@ -1406,7 +1406,7 @@ }; gpu-5 { - polling-delay-passive = <0>; + polling-delay-passive = <10>; polling-delay = <0>; thermal-sensors = <&tsens2 10>; @@ -1569,7 +1569,7 @@ }; mdmss-0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens3 1>; @@ -1628,7 +1628,7 @@ }; mdmss-1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens3 2>; @@ -1687,7 +1687,7 @@ }; mdmss-2 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens3 3>; @@ -1746,7 +1746,7 @@ }; mdmss-3 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens3 4>; diff --git a/qcom/tuna-vm-qrd.dtsi b/qcom/tuna-vm-qrd.dtsi index 1510613d..409ab94f 100644 --- a/qcom/tuna-vm-qrd.dtsi +++ b/qcom/tuna-vm-qrd.dtsi @@ -1,7 +1,29 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &soc { }; + +&qupv3_se4_spi { + status = "ok"; + qcom,touch-active = "st,fts"; + + st_fts@0 { + compatible = "st,fts"; + reg = <0x0>; + + st,touch-type = "primary"; + st,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <658>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0 + &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; + + }; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 08646728..9f46b027 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2847,6 +2847,12 @@ peer-name = <4>; }; + gh-rm-booster { + compatible = "qcom,gh-rm-booster"; + qcom,rm-vmid = <255>; + qcom,rm-affinity-default = <0>; + }; + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring { size = <0x4000>; gunyah-label = <0x11>;