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ARM: dts: qcom: Enable UFS MCQ on Kera platforms

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Enable the UFS MCQ feature on the Kera platforms.

Change-Id: I3e6349010c442666bef9a7b7c24dcd22e9d717b4
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
This commit is contained in:
Manish Pandey
2025-01-06 11:45:00 +05:30
parent acfa9db83b
commit 8edd785e2f
1 changed files with 11 additions and 3 deletions
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14
qcom/kera.dtsi
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@@ -2579,8 +2579,10 @@
ufshc_mem: ufshc@1d84000 { ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc"; compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>, reg = <0x1d84000 0x3000>,
<0x1d88000 0x18000>; <0x1d88000 0x18000>,
reg-names = "ufs_mem", "ice"; <0x1da5000 0x2000>,
<0x1da4000 0x10>;
reg-names = "ufs_mem", "ice", "mcq_sqd", "mcq_vs";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>; phys = <&ufsphy_mem>;
phy-names = "ufsphy"; phy-names = "ufsphy";
@@ -2588,6 +2590,10 @@
qcom,ice-use-hwkm; qcom,ice-use-hwkm;
qcom,prime-mask = <0x80>;
qcom,silver-mask = <0x07>;
qcom,esi-affinity-mask = <6 5 5 7 7 7 6 6>;
lanes-per-direction = <2>; lanes-per-direction = <2>;
clock-names = clock-names =
"core_clk", "core_clk",
@@ -2628,7 +2634,9 @@
depends-on-supply = <&apps_smmu>; depends-on-supply = <&apps_smmu>;
iommus = <&apps_smmu 0x60 0x0>; iommus = <&apps_smmu 0x60 0x0>;
qcom,iommu-dma = "bypass"; qcom,iommu-dma = "fastmap";
msi-parent = <&gic_its 0x60>;
qcom,iommu-msi-size = <0x1000>;
memory-region = <&ufshc_dma_resv>; memory-region = <&ufshc_dma_resv>;
shared-ice-cfg = <&ice_cfg>; shared-ice-cfg = <&ice_cfg>;
dma-coherent; dma-coherent;