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ARM: dts: msm: Update Tuna GPU

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Enable cx_host_irq, genPD and update bus frequency
for Tuna GPU.

Change-Id: I192fccfe65191ea73d4be4cdca245d65830acc0e
Signed-off-by: SIVA MULLATI <quic_smullati@quicinc.com>
This commit is contained in:
SIVA MULLATI
2024-10-29 14:48:25 +05:30
committed by Vishvanath Singh
parent f2f44ab4ad
commit 8e45dbe4a7
2 changed files with 30 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
gpu/tuna-gpu-pwrlevels.dtsi
View File

@@ -19,9 +19,9 @@
qcom,gpu-freq = <1050000000>; qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <9>; qcom,bus-freq = <11>;
qcom,bus-min = <9>; qcom,bus-min = <11>;
qcom,bus-max = <9>; qcom,bus-max = <11>;
}; };
/* Turbo */ /* Turbo */
@@ -30,9 +30,9 @@
qcom,gpu-freq = <937000000>; qcom,gpu-freq = <937000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>; qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <9>; qcom,bus-freq = <10>;
qcom,bus-min = <8>; qcom,bus-min = <9>;
qcom,bus-max = <9>; qcom,bus-max = <10>;
}; };
/* Nom_L1 */ /* Nom_L1 */
@@ -41,7 +41,7 @@
qcom,gpu-freq = <873000000>; qcom,gpu-freq = <873000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <8>; qcom,bus-freq = <9>;
qcom,bus-min = <7>; qcom,bus-min = <7>;
qcom,bus-max = <9>; qcom,bus-max = <9>;
}; };
@@ -52,9 +52,9 @@
qcom,gpu-freq = <763000000>; qcom,gpu-freq = <763000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>; qcom,bus-freq = <8>;
qcom,bus-min = <6>; qcom,bus-min = <7>;
qcom,bus-max = <8>; qcom,bus-max = <9>;
}; };
/* SVS_L2 */ /* SVS_L2 */
@@ -63,9 +63,9 @@
qcom,gpu-freq = <688000000>; qcom,gpu-freq = <688000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>; qcom,bus-freq = <6>;
qcom,bus-min = <5>; qcom,bus-min = <4>;
qcom,bus-max = <8>; qcom,bus-max = <7>;
}; };
/* SVS_L1 */ /* SVS_L1 */
@@ -74,9 +74,9 @@
qcom,gpu-freq = <644000000>; qcom,gpu-freq = <644000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>; qcom,bus-freq = <6>;
qcom,bus-min = <4>; qcom,bus-min = <4>;
qcom,bus-max = <8>; qcom,bus-max = <7>;
}; };
/* SVS */ /* SVS */
@@ -87,7 +87,7 @@
qcom,bus-freq = <4>; qcom,bus-freq = <4>;
qcom,bus-min = <2>; qcom,bus-min = <2>;
qcom,bus-max = <7>; qcom,bus-max = <6>;
}; };
/* Low_SVS */ /* Low_SVS */

24
gpu/tuna-gpu.dtsi
View File

@@ -23,11 +23,15 @@
reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc",
"qdss_gfx", "qdss_etr", "qdss_tmc"; "qdss_gfx", "qdss_etr", "qdss_tmc";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 80 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "kgsl_3d0_irq"; interrupt-names = "kgsl_3d0_irq", "cx_host_irq";
clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>; clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>,
clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb"; <&gpucc GPU_CC_AHB_CLK>,
<&aoss_qmp QDSS_CLK>;
clock-names = "gcc_gpu_memnoc_gfx",
"gpu_cc_ahb",
"apb_pclk";
qcom,gpu-model = "Adreno825"; qcom,gpu-model = "Adreno825";
@@ -56,7 +60,7 @@
<MHZ_TO_KBPS(3187, 4)>, /* NOM index=8 */ <MHZ_TO_KBPS(3187, 4)>, /* NOM index=8 */
<MHZ_TO_KBPS(3686, 4)>, /* TURBO index=9 */ <MHZ_TO_KBPS(3686, 4)>, /* TURBO index=9 */
<MHZ_TO_KBPS(4224, 4)>, /* TURBO_L1 index=10 */ <MHZ_TO_KBPS(4224, 4)>, /* TURBO_L1 index=10 */
<MHZ_TO_KBPS(4761, 4)>; /* TURBO_L3 index=11 */ <MHZ_TO_KBPS(4761, 4)>; /* TURBO_L2 index=11 */
zap-shader { zap-shader {
memory-region = <&gpu_microcode_mem>; memory-region = <&gpu_microcode_mem>;
@@ -111,7 +115,7 @@
compatible = "qcom,kgsl-smmu-v2"; compatible = "qcom,kgsl-smmu-v2";
reg = <0x3da0000 0x40000>; reg = <0x3da0000 0x40000>;
vddcx-supply = <&gpu_cc_cx_gdsc>; power-domains = <&gpucc GPU_CC_CX_GDSC>;
gfx3d_user: gfx3d_user { gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb"; compatible = "qcom,smmu-kgsl-cb";
@@ -144,10 +148,10 @@
<0 305 IRQ_TYPE_LEVEL_HIGH>; <0 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu"; interrupt-names = "hfi", "gmu";
regulator-names = "vddcx", "vdd"; power-domains = <&gpucc GPU_CC_CX_GDSC>,
<&gpucc GPU_CC_CX_GMU_GDSC>,
vddcx-supply = <&gpu_cc_cx_gdsc>; <&gxclkctl GX_CLKCTL_GX_GDSC>;
vdd-supply = <&gx_clkctl_gx_gdsc>; power-domain-names = "cx", "gmu_cx", "gx";
clocks = <&gpucc GPU_CC_CX_GMU_CLK>, clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>, <&gpucc GPU_CC_CXO_CLK>,