From 8e42a691cee6709d951f8c9cb413ca48c49c730c Mon Sep 17 00:00:00 2001
From: Manish Pandey <quic_mapa@quicinc.com>
Date: Thu, 5 Dec 2024 14:34:06 +0530
Subject: [PATCH] ARM: dts: msm: Update ref_clk_src for kera UFS 2.x platforms

Update ref_clk_src to source 19.2MHz clock to UFS 2.x Platforms.

Change-Id: I0f8a2307bc700a4eac2caa5e9ff5d0bfaac1b163
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
---
 qcom/kera_ufs2.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/qcom/kera_ufs2.dtsi b/qcom/kera_ufs2.dtsi
index 1ed18475..320ed23f 100644
--- a/qcom/kera_ufs2.dtsi
+++ b/qcom/kera_ufs2.dtsi
@@ -2,6 +2,9 @@
 /*
  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
+#include <dt-bindings/clock/qcom,gcc-kera.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
 
 &ufsphy_mem {
 	compatible = "qcom,ufs-phy-qmp-v4-niobe";
@@ -21,6 +24,20 @@
 	vdda-qref-supply = <&L2B>;
 	vdda-qref-max-microamp = <1890>;
 
+	clock-names =	"ref_clk_src",
+			"ref_aux_clk", "qref_clk",
+			"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
+			"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
+	clocks = <&rpmhcc RPMH_CXO_CLK>,
+		 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+		 <&tcsrcc TCSR_UFS_CLKREF_EN>,
+		 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
+		 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
+		 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
+		 <&ufs_phy_rx_symbol_0_clk>,
+		 <&ufs_phy_rx_symbol_1_clk>,
+		 <&ufs_phy_tx_symbol_0_clk>;
+
 	status = "ok";
 };