Merge "ARM: dts: qcom: keep the DT format aligned for SDCC"

This commit is contained in:
qctecmdr
2023-12-03 19:35:10 -08:00
committed by Gerrit - the friendly Code Review server

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@@ -42,7 +42,7 @@
serial0 = &qupv3_se7_2uart; serial0 = &qupv3_se7_2uart;
hsuart0 = &qupv3_se14_4uart; hsuart0 = &qupv3_se14_4uart;
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
sdhc2 = &sdhc_2; mmc1 = &sdhc_2; /* SDC2 SD card slot */
}; };
firmware: firmware { }; firmware: firmware { };
@@ -2117,13 +2117,13 @@
opp-100000000 { opp-100000000 {
opp-hz = /bits/ 64 <100000000>; opp-hz = /bits/ 64 <100000000>;
opp-peak-kBps = <160000 100000>; opp-peak-kBps = <160000 100000>;
opp-avg-kBps = <80000 50000>; opp-avg-kBps = <50000 0>;
}; };
opp-202000000 { opp-202000000 {
opp-hz = /bits/ 64 <202000000>; opp-hz = /bits/ 64 <202000000>;
opp-peak-kBps = <200000 120000>; opp-peak-kBps = <200000 120000>;
opp-avg-kBps = <80000 50000>; opp-avg-kBps = <104000 0>;
}; };
}; };
@@ -2139,7 +2139,7 @@
compatible = "qcom,sdhci-msm-v5"; compatible = "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>; reg = <0x08804000 0x1000>;
reg-names = "hc_mem"; reg-names = "hc";
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
@@ -2165,6 +2165,8 @@
iommus = <&apps_smmu 0x540 0x0>; iommus = <&apps_smmu 0x540 0x0>;
qcom,iommu-dma = "fastmap"; qcom,iommu-dma = "fastmap";
dma-coherent; dma-coherent;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc <&gem_noc MASTER_APPSS_PROC &config_noc