From 0c7716908d81ccedf8fbb8195b53a5052a249ac0 Mon Sep 17 00:00:00 2001
From: Melody Olvera <quic_molvera@quicinc.com>
Date: Fri, 22 Sep 2023 15:52:36 -0700
Subject: [PATCH] dt-bindings: Add snapshot of gic interrupt router
 documentation

Snapshot the gic interrupt router documentation from
qcom-6.1 commit e3266c8e04f8 ("dt-bindings: Add device-tree
bindings for gic-interrupt-router").

Change-Id: I5ad2acfe88680f77d85131bd52383674d118bcd3
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 .../soc/qcom/qcom,gic-interrupt-router.yaml   | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 bindings/soc/qcom/qcom,gic-interrupt-router.yaml

diff --git a/bindings/soc/qcom/qcom,gic-interrupt-router.yaml b/bindings/soc/qcom/qcom,gic-interrupt-router.yaml
new file mode 100644
index 00000000..e3aabff8
--- /dev/null
+++ b/bindings/soc/qcom/qcom,gic-interrupt-router.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,gic-interrupt-router.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. GIC Interrupt Router
+
+description: |
+  The ARM GIC peripheral supports "1 of N" selection of SPI interrupts. CPUs
+  may be classified as class0 and/or class1 and SPIs may be routed to any CPU
+  in a particular class.
+
+properties:
+  compatible:
+    const: "qcom,gic-intr-routing"
+    Usage: required
+
+  qcom,gic-class0-cpus:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: List of CPUs in GIC class 0.
+
+  qcom,gic-class1-cpus:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: List of CPUs in GIC class 1.
+
+examples:
+  - |
+    qcom,gic-interrupt-router {
+      compatible = "qcom,gic-intr-routing";
+      qcom,gic-class0-cpus = <0 1 2 3>;
+      qcom,gic-class1-cpus = <4 5 6 7>;
+    };
+...