From 8d7f1a22a8fd8063710eba9b2740abfa42bf8071 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 25 Sep 2024 12:26:45 +0530 Subject: [PATCH] ARM: dts: msm: Update videocc clock node as GenPD provider on Kera Mark videocc clock node as GenPD provider and disable the video GDSC regulator nodes for kera platform. While at it, keep the gdsc's as it is on kera-rumi platform. Change-Id: I4a41aacbaa7d144f72db48b9af3a336a92ef95aa Signed-off-by: Anaadi Mishra --- qcom/kera-rumi.dtsi | 8 ++++++++ qcom/kera.dtsi | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 8e1cfa60..76d7f98c 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -164,3 +164,11 @@ clock-output-names = "rpmh_clocks"; clock-frequency = <19200000>; }; + +&video_cc_mvs0_gdsc { + status = "ok"; +}; + +&video_cc_mvs0c_gdsc { + status = "ok"; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 05843866..4018f135 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1872,6 +1872,7 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_CX_LEVEL>; vdd_mxc-supply = <&VDD_MX_LEVEL>; + vdd_mm_mxc_voter-supply = <&VDD_CX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, @@ -1882,6 +1883,7 @@ "iface"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; qti,smmu-proxy { @@ -3233,14 +3235,12 @@ &video_cc_mvs0_gdsc { clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; - status = "ok"; }; &video_cc_mvs0c_gdsc { clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &reserved_memory {