samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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ARM: dts: msm: Replace swr nodes

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Replace swr node with default as swr core does not detect.

Change-Id: Ibe40453c70867c9687bd01ca9345dae8080bafac
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
This commit is contained in:
Ravulapati Vishnu Vardhan Rao
2024-11-27 18:44:26 +05:30
committed by Vishnuvardhan Rao Ravulapati
parent fded148f66
commit 8c9dc8e8bc
8 changed files with 19 additions and 19 deletions
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2
kera-audio-atp.dtsi
View File

@@ -21,7 +21,7 @@
qcom,wsa-max-devs = <0>; qcom,wsa-max-devs = <0>;
}; };
&wsa_swr { &swr0 {
qcom,swr-num-dev = <0>; qcom,swr-num-dev = <0>;
}; };

2
kera-audio-cdp.dtsi
View File

@@ -58,7 +58,7 @@
status = "okay"; status = "okay";
}; };
&wsa_swr { &swr0 {
wsa884x_0220: wsa884x@02170220 { wsa884x_0220: wsa884x@02170220 {
status = "okay"; status = "okay";
}; };

6
kera-audio-lpass-reg.dtsi
View File

@@ -6,7 +6,7 @@
reg = <0x6AC0000 0x0>; reg = <0x6AC0000 0x0>;
}; };
&rx_swr { &swr1 {
swrm-io-base = <0x6AD0000 0x0>; swrm-io-base = <0x6AD0000 0x0>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
}; };
@@ -19,12 +19,12 @@
reg = <0x6B00000 0x0>; reg = <0x6B00000 0x0>;
}; };
&wsa_swr { &swr0 {
swrm-io-base = <0x6B10000 0x0>; swrm-io-base = <0x6B10000 0x0>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
}; };
&tx_swr { &swr2 {
reg = <0x7630000 0x0>; reg = <0x7630000 0x0>;
}; };

4
kera-audio-mtp-qmp1000.dtsi
View File

@@ -5,7 +5,7 @@
#include "kera-audio-mtp.dtsi" #include "kera-audio-mtp.dtsi"
&rx_swr { &swr1 {
qcom,swr-num-dev = <2>; qcom,swr-num-dev = <2>;
}; };
@@ -33,7 +33,7 @@
status = "disabled"; status = "disabled";
}; };
&tx_swr { &swr2 {
qmp01: qmp@04170232 { qmp01: qmp@04170232 {
/* /*
* reg = <Class_partID[7:0] * reg = <Class_partID[7:0]

4
kera-audio-mtp.dtsi
View File

@@ -30,11 +30,11 @@
}; };
}; };
&rx_swr { &swr1 {
qcom,swr-num-dev = <2>; qcom,swr-num-dev = <2>;
}; };
&wsa_swr { &swr0 {
qcom,swr-num-dev = <2>; qcom,swr-num-dev = <2>;
}; };

6
kera-audio-overlay.dtsi
View File

@@ -37,7 +37,7 @@
qcom,use-clk-id = <VA_CORE_CLK>; qcom,use-clk-id = <VA_CORE_CLK>;
qcom,is-used-swr-gpio = <1>; qcom,is-used-swr-gpio = <1>;
qcom,va-swr-gpios = <&va_swr_gpios>; qcom,va-swr-gpios = <&va_swr_gpios>;
tx_swr: va_swr_master { swr2: va_swr_master {
compatible = "qcom,swr-mstr"; compatible = "qcom,swr-mstr";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <0>; #size-cells = <0>;
@@ -93,7 +93,7 @@
qcom,default-clk-id = <RX_TX_CORE_CLK>; qcom,default-clk-id = <RX_TX_CORE_CLK>;
clock-names = "rx_mclk2_2x_clk"; clock-names = "rx_mclk2_2x_clk";
clocks = <&clock_audio_rx_mclk2_2x_clk 0>; clocks = <&clock_audio_rx_mclk2_2x_clk 0>;
rx_swr: rx_swr_master { swr1: rx_swr_master {
compatible = "qcom,swr-mstr"; compatible = "qcom,swr-mstr";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <0>; #size-cells = <0>;
@@ -152,7 +152,7 @@
qcom,thermal-max-state = <11>; qcom,thermal-max-state = <11>;
qcom,noise-gate-mode = <2>; qcom,noise-gate-mode = <2>;
#cooling-cells = <2>; #cooling-cells = <2>;
wsa_swr: wsa_swr_master { swr0: wsa_swr_master {
compatible = "qcom,swr-mstr"; compatible = "qcom,swr-mstr";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <0>; #size-cells = <0>;

2
kera-audio-qrd.dtsi
View File

@@ -29,7 +29,7 @@
}; };
}; };
&wsa_swr { &swr0 {
wsa884x_0220: wsa884x@02170220 { wsa884x_0220: wsa884x@02170220 {
status = "disabled"; status = "disabled";
}; };

12
kera-audio.dtsi
View File

@@ -135,7 +135,7 @@
}; };
va_macro: va-macro@7660000 { va_macro: va-macro@7660000 {
tx_swr: va_swr_master { swr2: va_swr_master {
}; };
}; };
@@ -143,12 +143,12 @@
}; };
rx_macro: rx-macro@6AC0000 { rx_macro: rx-macro@6AC0000 {
rx_swr: rx_swr_master { swr1: rx_swr_master {
}; };
}; };
wsa_macro: wsa-macro@6B00000 { wsa_macro: wsa-macro@6B00000 {
wsa_swr: wsa_swr_master { swr0: wsa_swr_master {
}; };
}; };
@@ -175,9 +175,9 @@
}; };
&aliases { &aliases {
wsa_swr = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master"; swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master";
rx_swr = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000/rx_swr_master"; swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000/rx_swr_master";
tx_swr = "/soc/spf_core_platform/lpass-cdc/va-macro@7660000/va_swr_master"; swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@7660000/va_swr_master";
swr4 = "/soc/spf_core_platform/lpass_bt_swr@6CA0000/bt_swr_mstr"; swr4 = "/soc/spf_core_platform/lpass_bt_swr@6CA0000/bt_swr_mstr";
}; };