From ede1e06af139fba94ad5e040c7604e361ec0c993 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 25 Feb 2025 17:23:17 +0530 Subject: [PATCH 1/4] ARM: dts: msm: Update PHY timings for CMD VTDR panels on Kera CDP/RCM This update adjusts the PHY timings for the VTDR command mode panel on Kera RCM/CDP platforms based on the required FPS, following the removal of the qcom,mdss-dsi-panel-clockrate hardcoding. Previously, the hardcoding resulted in uniform panel PHY timings across all FPS. Some Kera RCMs have exhibited screen freeze issues when switching from 120 FPS to 60 FPS in command mode after the removal of the hardcoded clock rate. Interestingly, this issue has not been observed on Kera CDPs and other platforms, suggesting potential underlying hardware differences between CDPs and RCMs that necessitate proper tuning of panel PHY timings. Update the panel PHY timings to fix this. Fixes: I1c3c77eed76 ("ARM: dts: msm: remove hard coded panel clk rate for kera RCM"). Change-Id: Iffd1d5da485d6961baa49ff96a65882c491a8ff6 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-display-cdp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index 0dca9ffd..faa2551e 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -67,14 +67,20 @@ timing@1 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; }; timing@2 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; }; timing@3 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; }; }; }; @@ -111,10 +117,14 @@ timing@1 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; }; timing@2 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; }; }; }; @@ -151,6 +161,8 @@ timing@1 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; }; }; }; From bb0164b4b0f6eaad55d280889e7c85c0e7b3314b Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Thu, 13 Feb 2025 11:13:37 +0530 Subject: [PATCH 2/4] ARM: dts: msm: add ulps & roi support for 120hz VTDR6130 panel on Kera Add ulps and roi support for 120hz, 90hz & 60hz VTDR6130 panel on Kera target. Change-Id: I21bf599aadc6d4f10d25c3f1d232c1ba37a0d8b1 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-display.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index 5b448fb8..5bf58b4f 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -116,6 +116,34 @@ }; }; +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,ulps-enabled; +}; + &dsi_vtdr6130_amoled_qsync_144hz_cmd { qcom,ulps-enabled; }; From 914167ae87124023769400f9d026984b015cd3df Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Tue, 10 Dec 2024 14:52:46 +0800 Subject: [PATCH 3/4] ARM: dts: msm: update dvdd initial voltage for tuna QRD Increase dvdd initial voltage from 1.06v to 1.09v to avoid voltage drop issue caused by IR on tuna QRD target. Change-Id: I23bc8d44ec13260b9281e3c08968daa5e97fafb6 Signed-off-by: Lei Chen Signed-off-by: lnxdisplay --- display/tuna-sde-display-qrd.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi index 1ffc9332..312952ed 100644 --- a/display/tuna-sde-display-qrd.dtsi +++ b/display/tuna-sde-display-qrd.dtsi @@ -5,6 +5,17 @@ #include "tuna-sde-display.dtsi" +&L3D { + qcom,init-voltage = <1090000>; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1090000>; + qcom,supply-max-voltage = <1100000>; + }; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; From 70a86b3f2de3d7dd35a31efe4002891f59d9a703 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Mon, 10 Mar 2025 10:59:21 +0800 Subject: [PATCH 4/4] ARM: dts: msm: enable esd check for sharp qhd panel This change enables esd check for sharp qhd panel. Change-Id: I8cd0d670bbb71492b665b1a52a48a08848f90c0f Signed-off-by: Jinfeng Gu Signed-off-by: lnxdisplay --- display/sun-sde-display-common.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index a6b1b5b2..fffb51e2 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -796,6 +796,14 @@ &dsi_sharp_qhd_plus_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x07>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { timing@0 { /* 120 FPS */ qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 @@ -812,6 +820,13 @@ qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { timing@0 { /* 120 FPS */ qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07