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ARM: dts: msm: add 60hz and 90hz support for VTDR6130 panel on tuna

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Add 60hz and 90hz support for VTDR6130 panel on tuna target.

Change-Id: Iad6d7514f241be42bf2cd8addaefa2d3fb1e89a8
Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
This commit is contained in:
Abhinav Saurabh
2025-01-20 12:14:52 +05:30
committed by lnxdisplay
parent 41793be5f5
commit 8aebb5a491
2 changed files with 164 additions and 0 deletions
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56
display/tuna-sde-display-cdp.dtsi
View File

@@ -76,7 +76,9 @@
&dsi_vtdr6130_amoled_120hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
@@ -228,7 +230,61 @@
&dsi_vtdr6130_amoled_120hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_90hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_90hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_60hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_60hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;

108
display/tuna-sde-display-common.dtsi
View File

@@ -33,6 +33,10 @@
#include "dsi-panel-sim-video.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi"
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi"
@@ -305,6 +309,110 @@
};
};
&dsi_vtdr6130_amoled_90hz_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
05 06 02 04 00 12 0a];
qcom,display-topology = <2 2 1>,
<1 1 1>;
qcom,default-topology-index = <0>;
};
timing@1 {
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
05 06 02 04 00 12 0a];
qcom,display-topology = <2 2 1>,
<1 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_vtdr6130_amoled_90hz_video {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
05 06 02 04 00 12 0a];
qcom,display-topology = <2 2 1>,
<1 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_vtdr6130_amoled_60hz_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04
04 03 02 04 00 0d 09];
qcom,display-topology = <2 2 1>,
<1 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_vtdr6130_amoled_60hz_video {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04
04 03 02 04 00 0d 09];
qcom,display-topology = <2 2 1>,
<1 1 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,esd-check-enabled;