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Merge "dt-bindings: Add QUSB & USB BAM on dt-bindings"

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QCTECMDR Service
2025-04-03 13:24:30 -07:00
committed by Gerrit - the friendly Code Review server
parent ae152d193e 53765c8d58
commit 88c7784f2b
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189
bindings/soc/qcom/qcom,usb-bam.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,usb-bam.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MSM USB Bus Access Manager (BAM)
maintainers:
- Abdul Salam <quic_asalam@quicinc.com>
description:
This describes the device used to interface the USB controller
with the Smart Peripheral Subsystem (SPS). The BAM serves to
connect USB directly with other peer peripherals in the system
and is statically configured with a number of unidirectional pipes.
properties:
compatible:
const: qcom,usb-bam-msm
reg:
description: pair of physical base addresses and region size of BAM device
interrupts:
description: IRQ line for BAM device
maxItems: 1
qcom,usb-bam-num-pipes:
description: max number of pipes that can be used
qcom,usb-bam-fifo-baseaddr:
description: |
base address for bam pipe's data and descriptor
fifos. This can be on chip memory (ocimem). This
property is required if sub-node's mem-type is ocimem or usb private mem.
qcom,disable-clk-gating:
description: If present then disable BAM clock gating.
qcom,usb-bam-override-threshold:
description: |
If present then the default 512 byte threshold
is overridden. This threshold configures the threshold value for Read/Write
event generation by the BAM towards another BAM.
qcom,usb-bam-max-mbps-highspeed:
description: |
max mbps in high speed connection
for either rx or tx direction.
qcom,usb-bam-max-mbps-superspeed:
description: |
max mbps in super speed connection
for either rx or tx direction.
qcom,reset-bam-on-connect:
description: |
If present then BAM is RESET before connecting
pipe. This may be required if BAM peripheral is also reset before connect.
qcom,reset-bam-on-disconnect:
description: If present then BAM is RESET after disconnecting pipes.
required:
- compatible
- reg
- interrupts
- qcom,usb-bam-num-pipes
additionalProperties: false
patternProperties:
"^qcom,pipe[0-9]+$":
type: object
description: A number of USB BAM pipe parameters are represented as sub-nodes
properties:
label:
description: |
a string describing uniquely the usb bam pipe. The string can be
constracted as follows- <core>-<peer>-<direction>-<pipe num>.
core options- hsusb, ssusb/dwc3, hsic
peer options- qdss, ipa
direction options- in (from peer to usb), out (from usb to peer)
pipe num options- 0..127
qcom,usb-bam-mem-type:
description: |
Type of memory used by this PIPE. Can be one of
0 - Uses SPS's dedicated pipe memory
1 - System RAM allocated by driver
2 - OCI memory residing @ 'qcom,usb-bam-fifo-baseaddr'
qcom,dir:
description: |
pipe direction
0 - from usb (out)
1 - to usb (in)
qcom,pipe-num:
description: pipe number
qcom,peer-bam:
description: |
peer BAM can be one of
0 - QDSS_P_BAM
1 - IPA_P_BAM
qcom,data-fifo-size:
description: data fifo size
qcom,descriptor-fifo-size:
description: descriptor fifo size
qcom,peer-bam-physical-address:
description: |
peer BAM's physical address.
Not specified for IPA and used only for qdss connection
qcom,dst-bam-pipe-index:
description: destination BAM pipe index
qcom,src-bam-pipe-index:
description: source BAM pipe index
qcom,data-fifo-offset:
description: data fifo offset address
qcom,descriptor-fifo-offset:
description: descriptor fifo offset address
qcom,pipe-connection-type:
description: |
type of pipe connection. Can be one of
0 - BAM2BAM (default if not specified)
1 - SYS2BAM (only supported on UL)
required:
- label
- qcom,usb-bam-mem-type
- qcom,dir
- qcom,pipe-num
- qcom,peer-bam
- qcom,data-fifo-size
- qcom,descriptor-fifo-size
additionalProperties: false
examples:
- |
qcom,usbbam@f9a44000 {
compatible = "qcom,usb-bam-msm";
reg = <0xf9a44000 0x11000>;
interrupts = <0 135 0>;
qcom,usb-bam-num-pipes = <16>;
qcom,ignore-core-reset-ack;
qcom,disable-clk-gating;
qcom,usb-bam-max-mbps-highspeed = <400>;
qcom,usb-bam-max-mbps-superspeed = <3600>;
qcom,bam-type = <1>;
qcom,bam-mode = <0>;
qcom,pipe0 {
label = "hsusb-ipa-out-0";
qcom,usb-bam-mem-type = <0>;
qcom,dir = <0>;
qcom,pipe-num = <0>;
qcom,peer-bam = <2>;
qcom,src-bam-pipe-index = <1>;
qcom,data-fifo-offset = <0x2200>;
qcom,data-fifo-size = <0x1e00>;
qcom,descriptor-fifo-offset = <0x2100>;
qcom,descriptor-fifo-size = <0x100>;
};
qcom,pipe1 {
label = "hsusb-ipa-in-0";
qcom,usb-bam-mem-type = <0>;
qcom,dir = <1>;
qcom,pipe-num = <0>;
qcom,peer-bam = <2>;
qcom,dst-bam-pipe-index = <0>;
qcom,data-fifo-offset = <0x300>;
qcom,data-fifo-size = <0x1e00>;
qcom,descriptor-fifo-offset = <0>;
qcom,descriptor-fifo-size = <0x300>;
};
};
...

228
bindings/usb/qcom,qusb2phy.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/qcom,qusb2phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Qualcomm USB Phy
maintainers:
- Udipto Goswami <quic_ugoswami@quicinc.com>
properties:
compatible:
enum:
- qcom,qusb2phy
- qcom,qusb2phy-v2
reg:
description: Address and length of the registers set for the phy.
minItems: 1
maxItems: 7
reg-names:
minItems: 1
items:
- const: qusb_phy_base
- const: eud_enable_reg
- const: efuse_addr
- const: refgen_north_bg_reg_addr
qcom,efuse-bit-pos:
description: External fuse register bit required for phy functionality.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,efuse-num-bits:
description: External fuse register number of bit to be read.
vdd-supply:
description: vdd supply for HSPHY digital circuit operation.
vdda18-supply:
description: 1.8 V for HSPHY.
vdda33-supply:
description: 3.3 V for HSPHY.
refgen-supply:
description: Refgen regulator required for phy to work.
qcom,vdd-voltage-level:
description: Voltage level of the vdd supply.
This is set to min value to vote from usb.
$ref: /schemas/types.yaml#/definitions/uint32-array
clocks:
description: |
A list of phandles to the phy clocks::
- ref_clk_src:: Reference clk source required for enumeration.
- ref_clk:: Reference clk required for enumeration.
minItems: 1
maxItems: 3
clock-names:
minItems: 1
items:
- const: ref_clk_src
- const: ref_clk
resets:
maxItems: 1
reset-names:
items:
- const: phy_reset
phy_type:
oneOf:
- items:
- const: utmi
- items:
- const: ulpi
qcom,qusb-phy-init-seq:
description: Phy Initialization sequence required for init.
items:
items:
-
description: address
-
description: value
qcom,qusb-phy-reg-offset:
description: Phy Register offsets required for probe.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
-
description: address
qcom,qusb-phy-host-init-seq:
description: Host mode phy initialization sequence required for init.
items:
items:
-
description: address
-
description: value
if:
properties:
compatible:
contains:
enum:
- qcom,qusb2phy-v2
then:
required:
- qcom,qusb-phy-reg-offset
- qcom,qusb-phy-host-init-seq
else:
properties:
qcom,qusb-phy-reg-offset: false
qcom,qusb-phy-host-init-seq: false
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- vdd-supply
- vdda18-supply
- vdda33-supply
- resets
- phy_type
- qcom,qusb-phy-init-seq
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-holi.h>
qusb2_phy0: qusb@162b000 {
compatible = "qcom,qusb2phy-v2";
reg = <0x162B000 0x114>,
<0x0162A000 0x1000>,
<0x1b40268 0x4>,
<0x0162f014 0x4>;
reg-names = "qusb_phy_base",
"eud_enable_reg",
"efuse_addr",
"refgen_north_bg_reg_addr";
qcom,efuse-bit-pos = <25>;
qcom,efuse-num-bits = <3>;
vdd-supply = <&L18A>;
vdda18-supply = <&L2A>;
vdda33-supply = <&L3A>;
refgen-supply = <&L22A>;
qcom,vdd-voltage-level = <0 880000 880000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>;
clock-names = "ref_clk_src", "ref_clk";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
phy_type= "utmi";
qcom,qusb-phy-reg-offset =
<0x240 /* QUSB2PHY_PORT_TUNE1 */
0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */
0x210 /* QUSB2PHY_PWR_CTRL1 */
0x230 /* QUSB2PHY_INTR_CTRL */
0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */
0x254 /* QUSB2PHY_TEST1 */
0x198 /* PLL_BIAS_CONTROL_2 */
0x27c /* QUSB2PHY_DEBUG_CTRL1 */
0x280 /* QUSB2PHY_DEBUG_CTRL2 */
0x284 /* QUSB2PHY_DEBUG_CTRL3 */
0x288 /* QUSB2PHY_DEBUG_CTRL4 */
0x2a0>; /* QUSB2PHY_STAT5 */
qcom,qusb-phy-init-seq =
/* <value reg_offset> */
<0x23 0x210 /* PWR_CTRL1 */
0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
0x7c 0x18c /* PLL_CLOCK_INVERTERS */
0x80 0x2c /* PLL_CMODE */
0x0a 0x184 /* PLL_LOCK_DELAY */
0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
0x40 0x194 /* PLL_BIAS_CONTROL_1 */
0x22 0x198 /* PLL_BIAS_CONTROL_2 */
0x21 0x214 /* PWR_CTRL2 */
0x08 0x220 /* IMP_CTRL1 */
0x58 0x224 /* IMP_CTRL2 */
0x45 0x240 /* TUNE1 */
0x29 0x244 /* TUNE2 */
0xca 0x248 /* TUNE3 */
0x04 0x24c /* TUNE4 */
0x03 0x250 /* TUNE5 */
0x30 0x23c /* CHG_CTRL2 */
0x22 0x210>; /* PWR_CTRL1 */
qcom,qusb-phy-host-init-seq =
/* <value reg_offset> */
<0x23 0x210 /* PWR_CTRL1 */
0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
0x7c 0x18c /* PLL_CLOCK_INVERTERS */
0x80 0x2c /* PLL_CMODE */
0x0a 0x184 /* PLL_LOCK_DELAY */
0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
0x40 0x194 /* PLL_BIAS_CONTROL_1 */
0x22 0x198 /* PLL_BIAS_CONTROL_2 */
0x21 0x214 /* PWR_CTRL2 */
0x08 0x220 /* IMP_CTRL1 */
0x58 0x224 /* IMP_CTRL2 */
0x45 0x240 /* TUNE1 */
0x29 0x244 /* TUNE2 */
0xca 0x248 /* TUNE3 */
0x04 0x24c /* TUNE4 */
0x03 0x250 /* TUNE5 */
0x30 0x23c /* CHG_CTRL2 */
0x22 0x210>; /* PWR_CTRL1 */
};