From 88a17ffa07b25e06184a0011b4b41fac4b7a070f Mon Sep 17 00:00:00 2001
From: Harshdeep Dhatt <quic_hdhatt@quicinc.com>
Date: Fri, 5 Jan 2024 15:58:06 -0700
Subject: [PATCH] dt-bindings: Add soccp controller property

This is needed to vote for soccp boot/slumber sequence for
hardware fence feature.

Change-Id: I169d83ed9d5acf66027194bf5fee0825bb5602d2
Signed-off-by: Harshdeep Dhatt <quic_hdhatt@quicinc.com>
---
 bindings/adreno-gmu.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/bindings/adreno-gmu.txt b/bindings/adreno-gmu.txt
index a5544793..08173ede 100644
--- a/bindings/adreno-gmu.txt
+++ b/bindings/adreno-gmu.txt
@@ -66,6 +66,7 @@ GMU GDSC/regulators:
 			baseAddr - base address of the IPC region
 			size     - size of the IPC region
 
+- qcom,soccp-controller: Phandle of the soccp controller
 
 Example: