Merge "ARM: dts: msm: Update initial DCVS devices for Kera"

This commit is contained in:
QCTECMDR Service
2025-02-05 17:55:16 -08:00
committed by Gerrit - the friendly Code Review server

View File

@@ -3150,7 +3150,7 @@
< 940800 547000 >,
< 1190400 1017000 >,
< 2208000 1708000 >,
< 2400000 2092000 >;
< 2361600 2092000 >;
};
ddr5-tbl {
@@ -3161,7 +3161,7 @@
< 1612800 1555000 >,
< 1824000 1708000 >,
< 2208000 2092000 >,
< 2400000 3196000 >;
< 2361600 4224000 >;
};
};
@@ -3175,8 +3175,8 @@
< 960000 547000 >,
< 1209600 1017000 >,
< 1459200 1555000 >,
< 1804800 1708000 >,
< 2304000 2092000 >;
< 1900800 1708000 >,
< 2630400 2092000 >;
};
ddr5-tbl {
@@ -3186,8 +3186,8 @@
< 1209600 768000 >,
< 1459200 1555000 >,
< 1651200 1708000 >,
< 1804800 2092000 >,
< 2304000 3196000 >;
< 1900800 2092000 >,
< 2630400 3196000 >;
};
};
@@ -3203,7 +3203,7 @@
< 1190400 768000 >,
< 1612800 1017000 >,
< 2208000 1708000 >,
< 2400000 2092000 >;
< 2361600 2092000 >;
};
ddr5-tbl {
@@ -3213,7 +3213,7 @@
< 1190400 768000 >,
< 1612800 1555000 >,
< 2208000 2092000 >,
< 2400000 3196000 >;
< 2361600 3196000 >;
};
};
@@ -3248,9 +3248,9 @@
qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 883200 350000 >,
< 1401600 533000 >,
< 2016000 600000 >;
< 902400 350000 >,
< 1497600 533000 >,
< 2054400 600000 >;
};
gold {
@@ -3262,9 +3262,9 @@
< 1190400 533000 >,
< 1401600 600000 >,
< 1824000 806000 >,
< 2803200 933000 >,
< 2918400 1066000 >,
< 3014400 1211000 >;
< 2534400 933000 >,
< 2707200 1066000 >,
< 2841600 1211000 >;
};
gold-compute {
@@ -3296,10 +3296,10 @@
< 1113600 998400 >,
< 1228800 1094400 >,
< 1344000 1209600 >,
< 1497600 1363200 >,
< 1497600 1344000 >,
< 1708800 1497600 >,
< 1804800 1516800 >,
< 2054400 1804800 >;
< 1843200 1593600 >,
< 2054400 1785600 >;
};
gold {
@@ -3308,14 +3308,14 @@
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 480000 364800 >,
< 940800 556800 >,
< 940800 518400 >,
< 1190400 710400 >,
< 1286400 902400 >,
< 1497600 1209600 >,
< 1708800 1363200 >,
< 1708800 1344000 >,
< 2073600 1497600 >,
< 2400000 1516800 >,
< 2707200 1804800 >;
< 2361600 1593600 >,
< 2707200 1785600 >;
};
prime {
@@ -3324,14 +3324,14 @@
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 480000 364800 >,
< 633600 556800 >,
< 633600 518400 >,
< 960000 806400 >,
< 1324800 998400 >,
< 1651200 1209600 >,
< 1766400 1363200 >,
< 2208000 1497600 >,
< 2496000 1516800 >,
< 2918400 1804800 >;
< 1766400 1344000 >,
< 2150400 1497600 >,
< 2496000 1593600 >,
< 2630400 1785600 >;
};
prime-compute {