From 86f0caef7cf0c1866378fa34edbdea6719a1ac0b Mon Sep 17 00:00:00 2001 From: Ronak Vijay Raheja Date: Wed, 28 Jun 2023 18:24:46 -0700 Subject: [PATCH] dt-bindings: Add USB QMP SSPHY bindings Add SuperSpeed USB QMP PHY bindings used on MSM platforms. Change-Id: Iad3f4a10b6425d3814446f882b086ca7dba96d01 Signed-off-by: Ronak Vijay Raheja --- bindings/usb/qcom,usb-ssphy-qmp.yaml | 229 +++++++++++++++++++++++++++ 1 file changed, 229 insertions(+) create mode 100644 bindings/usb/qcom,usb-ssphy-qmp.yaml diff --git a/bindings/usb/qcom,usb-ssphy-qmp.yaml b/bindings/usb/qcom,usb-ssphy-qmp.yaml new file mode 100644 index 00000000..13465acc --- /dev/null +++ b/bindings/usb/qcom,usb-ssphy-qmp.yaml @@ -0,0 +1,229 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,usb-ssphy-qmp.yaml## +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SuperSpeed USB QMP PHY + +maintainers: + - Ronak Vijay Raheja + +properties: + compatible: + items: + - enum: + - qcom,usb-ssphy-qmp + - qcom,usb-ssphy-qmp-v1 + - qcom,usb-ssphy-qmp-v2 + - qcom,usb-ssphy-qmp-usb3-or-dp + - qcom,usb-ssphy-qmp-dp-combo + + reg: + description: | + Address and length of the register set for the device. Required regs + are:: + - qmp_phy_base:: QMP PHY Base register set + Optional regs are:: + - tcsr_usb3_dp_phymode:: top-level CSR register to be written to + select super speed usb qmp phy + - pcs_clamp_enable_reg:: Clamps the phy data inputs and enables USB3 + autonomous mode. + - vls_clamp_reg:: top-level CSR register to be written to enable phy + vls clamp which allows phy to detect autonomous mode. + + reg-names: + minItems: 1 + items: + - const: qmp_phy_base # required + - const: tcsr_usb3_dp_phymode + - const: pcs_clamp_enable_reg + - const: vls_clamp_reg + + vdd-supply: + description: phandle to the Vdd supply for SSPHY digital circuit operation + + core-supply: + description: phandle to the high-voltage analog supply for SSPHY + + usb3_dp_phy_gdsc-supply: + description: | + phandle to the GDSC regulator device tree node related to USB QMP DP PHY. + + clocks: + minItems: 1 + items: + - description: GCC_USB3_PRIM_PHY_AUX_CLK clk + - description: GCC_USB3_PRIM_PHY_PIPE_CLK clk + - description: GCC_USB3_PRIM_PHY_PIPE_CLK_SRC clk + - description: usb3_phy_wrapper_gcc_usb30_pipe_clk clk + - description: RPMH_CXO_PAD_CLK clk + - description: TCSR_USB3_CLKREF_EN clk + - description: GCC_USB3_PRIM_PHY_COM_AUX_CLK clk + + clock-names: + minItems: 2 + items: + - const: aux_clk # required + - const: pipe_clk # required + - const: pipe_clk_mux + - const: pipe_clk_ext_src + - const: ref_clk_src + - const: ref_clk + - const: com_aux_clk + + qcom,vdd-voltage-level: + description: | + This property must be a list of three integer values (no, min, max) where + each value represents either a voltage in microvolts or a value + corresponding to voltage corner. + $ref: /schemas/types.yaml#/definitions/uint32-array + + resets: + description: | + Reset specifier pair consists of phandle for the reset controller and + reset lines used by this controller. + + reset-names: + description: | + reset signal name strings sorted in the same order as the resets + property. + + qcom,qmp-phy-init-seq: + description: | + QMP PHY initialization sequence with reg offset, its value, delay after + register write. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,qmp-phy-reg-offset: + description: | + Provides important phy register offsets in an order defined in the phy + driver. Provide below mentioned register offsets in order for non USB DP + combo PHY:: + - USB3_PHY_PCS_STATUS + - USB3_PHY_AUTONOMOUS_MODE_CTRL + - USB3_PHY_LFPS_RXTERM_IRQ_CLEAR + - USB3_PHY_POWER_DOWN_CONTROL + - USB3_PHY_SW_RESET + - USB3_PHY_START + In addion to above following set of registers offset needed for USB DP + combo PHY in mentioned order:: + - USB3_DP_DP_PHY_PD_CTL + - USB3_DP_COM_POWER_DOWN_CTRL + - USB3_DP_COM_SW_RESET + - USB3_DP_COM_RESET_OVRD_CTRL + - USB3_DP_COM_PHY_MODE_CTRL + - USB3_DP_COM_TYPEC_CTRL + - USB3_DP_COM_SWI_CTRL + Optional register for enabling/disabling VLS clamp if available:: + - USB3_PCS_MISC_CLAMP_ENABLE + Optional register for configuring USB Type-C port select if available:: + - USB3_PHY_PCS_MISC_TYPEC_CTRL + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,vbus-valid-override: + description: | + If present, indicates VBUS pin is not connected to the USB PHY and the + controller must rely on external VBUS notification in order to manually + relay the notification to the SSPHY. + + qcom,vdd-max-load-uA: + description: | + If present, indicates the maximum current (in uA) the PHY is expected to + draw from the vdd power supply. + + qcom,core-voltage-level: + description: | + This property must be a list of three integer values (no, min, max) where + each value represents either a voltage in microvolts or a value + corresponding to voltage corner. + + qcom,core-max-load-uA: + description: | + If present, indicates the maximum current (in uA) the PHY is expected to + draw from the core power supply. + + qcom,link-training-reset: + description: | + This property indicates to start link training timer to reset the elastic + buffer based on rx equalization value. + + extcon: + description: | + phandle to external connector devices which provide type-C based + "USB-HOST" cable events. This phandle is used for notifying number of + lanes used in case of USB+DP concurrent mode to driver. + +required: + - compatible + - reg + - reg-names + - vdd-supply + - core-supply + - clocks + - clock-names + - qcom,vdd-voltage-level + - resets + - reset-names + - qcom,qmp-phy-init-seq + - qcom,qmp-phy-reg-offset + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&pm_v6g_l3>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm_v8_l3>; + usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_default>; + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; +...