From 86ee38dfc0ee08a6daaf21cb9977798acf0951b4 Mon Sep 17 00:00:00 2001
From: Anaadi Mishra <quic_anaadim@quicinc.com>
Date: Wed, 21 Aug 2024 10:28:31 +0530
Subject: [PATCH] ARM: dts: msm: Update gpucc and gx_clkctl clock node as GenPD
 provider

Mark gpucc clock node as GenPD provider and disable the
graphics GDSC regulator nodes. Update gxclkctl
node to add support for gx_clkctl_gx_gdsc power domain.

While at it, keep the gdsc regulator nodes as it is on rumi platform.

Change-Id: If205c2116841ff3a11ebce4e06ca3067c4a8721b
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
---
 qcom/tuna-rumi.dtsi |  8 ++++++++
 qcom/tuna.dtsi      | 13 +++++++------
 2 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi
index 915c4926..b24a40a4 100644
--- a/qcom/tuna-rumi.dtsi
+++ b/qcom/tuna-rumi.dtsi
@@ -212,3 +212,11 @@
 &video_cc_mvs0c_gdsc {
 	status = "ok";
 };
+
+&gpu_cc_cx_gdsc {
+	status = "ok";
+};
+
+&gx_clkctl_gx_gdsc {
+	status = "ok";
+};
diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi
index a2a88aab..64e59129 100644
--- a/qcom/tuna.dtsi
+++ b/qcom/tuna.dtsi
@@ -1605,13 +1605,16 @@
 			      "gpll0_out_main_div";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		#power-domain-cells = <1>;
 	};
 
 	gxclkctl: clock-controller@3d68024 {
-		compatible = "qcom,dummycc";
-		clock-output-names = "gxclkctl_clocks";
-		#clock-cells = <1>;
-		#reset-cells = <1>;
+		compatible = "qcom,tuna-gx_clkctl";
+		reg = <0x3d68024 0x8>;
+		reg-name = "cc_base";
+		power-domains = <&gpucc GPU_CC_CX_GDSC>;
+		vdd_gx-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
+		#power-domain-cells = <1>;
 	};
 
 	tcsrcc: clock-controller@1fbf000 {
@@ -2632,12 +2635,10 @@
 &gpu_cc_cx_gdsc {
 	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
 	parent-supply = <&VDD_CX_LEVEL>;
-	status = "ok";
 };
 
 &gx_clkctl_gx_gdsc {
 	parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
-	status = "ok";
 };
 
 &video_cc_mvs0_gdsc {