Merge "ARM: dts: msm: Reserve 32kb to dcc on HLOS for kera" into kernel.lnx.6.6.r1-rel

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2025-01-08 02:12:51 -08:00
committed by Gerrit - the friendly Code Review server

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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/soc/qcom,dcc_v2.h>
@@ -20,13 +20,13 @@
dcc: dcc_v2@100ff000 {
compatible = "qcom,dcc-v2";
reg = <0x100ff000 0x1000>,
<0x10084000 0x4000>;
<0x10080000 0x8000>;
status = "disabled";
qcom,transaction_timeout = <0>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x4000>;
dcc-ram-offset = <0x0>;
};
mem_dump {