ARM: dts: msm: Remove jtag_mm node on monaco
Remove jtag_mm DT node as this feature is not enabled on monaco. Change-Id: I3fde6c254dbbdf9ced550fc53ba59a6e27866db0 Signed-off-by: Xiaoqi Zhuang <quic_xiaozhua@quicinc.com>
This commit is contained in:
@@ -1592,50 +1592,6 @@
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jtag_mm0: jtagmm@9040000 {
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/* compatible = "qcom,jtagv8-mm"; */
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reg = <0x9040000 0x1000>;
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reg-names = "etm-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <&CPU0>;
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};
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jtag_mm1: jtagmm@9140000 {
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/* compatible = "qcom,jtagv8-mm"; */
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reg = <0x9140000 0x1000>;
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reg-names = "etm-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <&CPU1>;
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};
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jtag_mm2: jtagmm@9240000 {
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/* compatible = "qcom,jtagv8-mm"; */
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reg = <0x9240000 0x1000>;
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reg-names = "etm-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <&CPU2>;
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};
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jtag_mm3: jtagmm@9340000 {
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/* compatible = "qcom,jtagv8-mm"; */
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reg = <0x9340000 0x1000>;
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reg-names = "etm-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "core_clk";
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qcom,coresight-jtagmm-cpu = <&CPU3>;
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};
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dcc: dcc_v2@16FF000 {
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dcc: dcc_v2@16FF000 {
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compatible = "qcom,dcc-v2";
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compatible = "qcom,dcc-v2";
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reg = <0x16FF000 0x1000>,
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reg = <0x16FF000 0x1000>,
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