From 77314aed5c76bc5c557b360f5221b6ede754ad05 Mon Sep 17 00:00:00 2001 From: Ronak Vijay Raheja Date: Wed, 17 Jan 2024 15:49:55 -0800 Subject: [PATCH 1/2] ARM: dts: msm: Use "iommu-addresses" property for sun Use upstream compatible device smmu address space DT property "iommu-addresses" in accordance to FR92369. Replace existing use of "qcom,iommu-dma-addr-pool" with "iommu-addresses" for dwc3 node in usb0 for describing to the DMA API what IOVA addresses dwc3 cannot use. Change-Id: Ia18d064649fb86e809023dbd61262c0e026acf73 Signed-off-by: Ronak Vijay Raheja --- qcom/sun-usb.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/sun-usb.dtsi b/qcom/sun-usb.dtsi index ee364302..6283afaa 100644 --- a/qcom/sun-usb.dtsi +++ b/qcom/sun-usb.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -57,13 +57,13 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ - dwc3@a600000 { + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0xa600000 0xd93c>; iommus = <&apps_smmu 0x40 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + iommu-addresses = <&dwc3_0 0x0 0x90000000>, <&dwc3_0 0xf0000000 0x10000000>; dma-coherent; interrupts = ; From 29471c0db8604d865252761621022267e53e6006 Mon Sep 17 00:00:00 2001 From: Ronak Vijay Raheja Date: Wed, 17 Jan 2024 16:29:12 -0800 Subject: [PATCH 2/2] ARM: dts: msm: Fix config values for QMP PHY Fix values for QMP PHY configs according to updates from Hardware Settings team which allow resolving Host mode enumeration issues for SuperSpeed devices. Change-Id: I4ad0ff3df8b8b8588679e93135aaac72c537015c Signed-off-by: Ronak Vijay Raheja --- qcom/sun-usb.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/qcom/sun-usb.dtsi b/qcom/sun-usb.dtsi index 6283afaa..5f3be9fa 100644 --- a/qcom/sun-usb.dtsi +++ b/qcom/sun-usb.dtsi @@ -234,11 +234,11 @@ USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x0C USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E - USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x22 - USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x12 - USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xDA - USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3F - USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB + USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x3F + USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF + USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xFF + USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xDF + USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xED USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x19 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x09 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x91 @@ -284,11 +284,11 @@ USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x0C USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E - USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x22 - USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x12 - USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xDA - USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3F - USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB + USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF + USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF + USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBF + USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xDF + USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xFD USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x19 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x09 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x91 @@ -305,16 +305,16 @@ USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 - USB3_DP_PCS_RX_SIGDET_LVL 0x99 + USB3_DP_PCS_RX_SIGDET_LVL 0x55 USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 USB3_DP_PCS_CDR_RESET_TIME 0x0A - USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 - USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 + USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0xD4 + USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x30 USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C USB3_DP_PCS_EQ_CONFIG1 0x4B USB3_DP_PCS_EQ_CONFIG5 0x10 - USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x68 + USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x7F USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40