From e9608835b6a4a2d46a77ea312722dec3d9177b07 Mon Sep 17 00:00:00 2001
From: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Date: Tue, 16 Jan 2024 15:17:46 -0800
Subject: [PATCH] ARM: dts: msm: Add LLCC broadacst register mappings on
 Pineapple

Add mappings for LLCC Broadcast_OR, Broadcast_AND regions on
Pineapple SoC.

Change-Id: Ic807d4e5c8e84b94957336acf71c98a6b870782f
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
---
 qcom/pineapple.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/qcom/pineapple.dtsi b/qcom/pineapple.dtsi
index a02c090a..73eaf0df 100644
--- a/qcom/pineapple.dtsi
+++ b/qcom/pineapple.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/clock/qcom,camcc-pineapple.h>
@@ -1851,9 +1851,9 @@
 		compatible = "qcom,pineapple-llcc", "qcom,llcc-v50";
 		reg = <0x25000000 0x200000>, <0x25400000 0x200000>,
 			<0x25200000 0x200000>, <0x25600000 0x200000>,
-			<0x25800000 0x200000>;
+			<0x25800000 0x200000>, <0x25a00000 0x200000>;
 		reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
-			"llcc3_base", "llcc_broadcast_base";
+			"llcc3_base", "llcc_broadcast_or_base", "llcc_broadcast_and_base";
 		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		cap-based-alloc-and-pwr-collapse;