ARM: dts: msm: add pmic-glink-debug PMIC subdevices for Sun boards

Add SMB and IDT charger PMIC devices inside of the pmic-glink-debug
device.  These are interfaced over I2C and an SPMI bridge bus.  This
ensures that software is able to access the registers of these PMICs.

Change-Id: I7afc56cb78a353960cb7db98ce5d9b51a05db9fe
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
This commit is contained in:
David Collins
2023-10-25 12:09:31 -07:00
parent 47e74e072e
commit 834840db5a
3 changed files with 97 additions and 0 deletions

View File

@@ -62,6 +62,33 @@
};
};
&pmic_glink_debug {
i2c@106 {
reg = <0x106>; /* I2C instance 6 in ADSP for SE5 */
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1501@68 {
compatible = "qcom,i2c-pmic";
reg = <0x68>;
qcom,can-sleep;
};
qcom,smb1501@69 {
compatible = "qcom,i2c-pmic";
reg = <0x69>;
qcom,can-sleep;
};
qcom,idt9418@3b {
compatible = "qcom,i2c-pmic";
reg = <0x3b>;
qcom,can-sleep;
};
};
};
&regulator_ocp_notifier {
periph-1c1-supply = <&L1B>;
periph-1c2-supply = <&L2B>;

View File

@@ -3,6 +3,8 @@
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/spmi/spmi.h>
#include "sun-qrd.dtsi"
&pmic_glink_adc {
@@ -38,3 +40,44 @@
label = "smb1396_2_die_temp";
};
};
&pmic_glink_debug {
i2c@106 {
reg = <0x106>; /* I2C instance 6 in ADSP for SE5 */
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1396@34 {
compatible = "qcom,i2c-pmic";
reg = <0x34>;
qcom,can-sleep;
};
qcom,smb1396@35 {
compatible = "qcom,i2c-pmic";
reg = <0x35>;
qcom,can-sleep;
};
qcom,idt9418@3b {
compatible = "qcom,i2c-pmic";
reg = <0x3b>;
qcom,can-sleep;
};
};
/* SPMI bridge bus 0 with SMB1510 device */
spmi@200 {
reg = <0x200>;
#address-cells = <2>;
#size-cells = <0>;
qcom,bus-type = "spmi";
qcom,smb1510@d {
compatible = "qcom,spmi-pmic";
reg = <0xd SPMI_USID>;
qcom,can-sleep;
};
};
};

View File

@@ -38,3 +38,30 @@
label = "smb1501_2_die_temp";
};
};
&pmic_glink_debug {
i2c@106 {
reg = <0x106>; /* I2C instance 6 in ADSP for SE5 */
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1501@68 {
compatible = "qcom,i2c-pmic";
reg = <0x68>;
qcom,can-sleep;
};
qcom,smb1501@69 {
compatible = "qcom,i2c-pmic";
reg = <0x69>;
qcom,can-sleep;
};
qcom,idt9418@3b {
compatible = "qcom,i2c-pmic";
reg = <0x3b>;
qcom,can-sleep;
};
};
};