From 82e81bc9070ce8b7944ae46f5856ae6aeb7bfcf7 Mon Sep 17 00:00:00 2001 From: Ziqi Chen Date: Tue, 2 Jan 2024 17:50:52 +0800 Subject: [PATCH] =?UTF-8?q?ARM:=20dts:=20qcom:=20use=20property=20?= =?UTF-8?q?=E2=80=9Ciommu-addresses=E2=80=9D=20for=20SDC2?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The upstream commit ("iommu: Implement of_iommu_get_resv_regions()") The upstream linux community has added a devicetree property "iommu-addresses", which describes to the DMA api what IOVA addresses a device can/cannot use. So we replace “qcom,iommu- dma-addr-pool” by “iommu-addresses” since kernel 6.5 to follow upstream. Change-Id: If18f14d6cb13aa2ed67c1417295fc30723b0c932 Signed-off-by: Ziqi Chen --- qcom/sun.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 1071b45f..40df802a 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2437,6 +2437,15 @@ qcom,client-id = <0x00000001>; }; + sdhc_2_dma_resv: sdhc_2_dma_resv_region { + /* + * Restrict IOVA mappings for SDHC2 buffers to the 256 MB region + * from 0x40000000 - 0x4fffffff. + */ + iommu-addresses = <&sdhc_2 0x0 0x40000000>, + <&sdhc_2 0x50000000 0xb0000000>; + }; + sdhc_2: sdhci@8804000 { status = "disabled"; @@ -2468,7 +2477,7 @@ iommus = <&apps_smmu 0x540 0x0>; qcom,iommu-dma = "fastmap"; dma-coherent; - qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + memory-region = <&sdhc_2_dma_resv>; qcom,iommu-geometry = <0x40000000 0x10000000>; interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,