From 8199522ad8fc29451a962b2f2904daca207333da Mon Sep 17 00:00:00 2001 From: Unnathi Chalicheemala Date: Mon, 2 Oct 2023 13:51:03 -0700 Subject: [PATCH] dt-bindings: msm: Change LLCC bindings for Pineapple and Sun Following device tree register addresses change from upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address used for accessing LLCC banks"). Change LLCC bindings for Pineapple and Sun SoC. Change-Id: I60bdfd7e4bc19343a3eb6a1c0c597523f1c30963 Signed-off-by: Unnathi Chalicheemala --- bindings/arm/msm/qcom,llcc.yaml | 54 ++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 11 deletions(-) diff --git a/bindings/arm/msm/qcom,llcc.yaml b/bindings/arm/msm/qcom,llcc.yaml index 7135418b..9142b3d8 100644 --- a/bindings/arm/msm/qcom,llcc.yaml +++ b/bindings/arm/msm/qcom,llcc.yaml @@ -32,17 +32,16 @@ properties: - qcom,sm8350-llcc - qcom,sm8450-llcc - qcom,sm8550-llcc + - qcom,pineapple-llcc - qcom,sun-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -52,15 +51,48 @@ required: - reg - reg-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,pineapple-llcc + - qcom,sun-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false examples: - | #include - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x01100000 0x50000>, <0x01180000 0x50000>, + <0x01200000 0x50000>, <0x01280000 0x50000>, + <0x1300000 0x50000> ; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = ; + }; };