ARM: dts: msm: Add trustedvm device tree files for Sun target
Add the trusted VM devicetree nodes for Sun target. Change-Id: I393576e742d0c793d26558e64a3f39102c1de032 Signed-off-by: Ramkumar Radhakrishnan <quic_rradhakr@quicinc.com> Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This commit is contained in:
Ramkumar Radhakrishnan
committed by
Rui Chen
Rui Chen
parent
a5e286170d
commit
7d485131a1
5
Kbuild
5
Kbuild
@@ -1,3 +1,4 @@
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ifneq ($(CONFIG_ARCH_QTI_VM), y)
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dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
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display/sun-sde-display-cdp-overlay.dtbo \
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display/sun-sde-display-mtp-overlay.dtbo \
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@@ -14,6 +15,10 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
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display/sun-sde-display-mtp-nfc-overlay.dtbo \
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display/sun-sde-display-cdp-v8-overlay.dtbo \
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display/sun-sde-display-mtp-v8-overlay.dtbo
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else
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dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \
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display/trustedvm-sun-sde-display-mtp-overlay.dtbo
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endif
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always-y := $(dtb-y) $(dtbo-y)
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subdir-y := $(dts-dirs)
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17
display/trustedvm-sun-sde-display-cdp-overlay.dts
Normal file
17
display/trustedvm-sun-sde-display-cdp-overlay.dts
Normal file
@@ -0,0 +1,17 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include "trustedvm-sun-sde.dtsi"
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#include "trustedvm-sun-sde-display-cdp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM";
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compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
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qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
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qcom,board-id = <0x10001 0>;
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};
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143
display/trustedvm-sun-sde-display-cdp.dtsi
Normal file
143
display/trustedvm-sun-sde-display-cdp.dtsi
Normal file
@@ -0,0 +1,143 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "trustedvm-sun-sde-display.dtsi"
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&dsi_vtdr6130_amoled_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
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};
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&dsi_vtdr6130_amoled_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
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};
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&dsi_vtdr6130_amoled_120hz_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_nt37801_amoled_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_nt37801_amoled_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_vtdr6130_amoled_120hz_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_sim_panel_au {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_vtdr6130_amoled_qsync_144hz_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_vtdr6130_amoled_qsync_144hz_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_sharp_4k_dsc_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
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};
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&dsi_sharp_4k_dsc_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
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};
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&dsi_sim_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_vid {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_dsc_375_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_dsc_10b_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_dual_sim_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,bl-dsc-cmd-state = "dsi_lp_mode";
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};
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&dsi_dual_sim_dsc_375_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_sec_hd_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <1023>;
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};
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&sde_dsi {
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qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
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};
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17
display/trustedvm-sun-sde-display-mtp-overlay.dts
Normal file
17
display/trustedvm-sun-sde-display-mtp-overlay.dts
Normal file
@@ -0,0 +1,17 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include "trustedvm-sun-sde.dtsi"
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#include "trustedvm-sun-sde-display-mtp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM";
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compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
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qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
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qcom,board-id = <0x10008 0>;
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};
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69
display/trustedvm-sun-sde-display-mtp.dtsi
Normal file
69
display/trustedvm-sun-sde-display-mtp.dtsi
Normal file
@@ -0,0 +1,69 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "trustedvm-sun-sde-display.dtsi"
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&dsi_nt37801_amoled_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_nt37801_amoled_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_sim_panel_au {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_sim_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_vid {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_dsc_375_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_dsc_10b_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_dual_sim_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,bl-dsc-cmd-state = "dsi_lp_mode";
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};
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&dsi_dual_sim_dsc_375_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_sec_hd_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <1023>;
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};
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&sde_dsi {
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qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
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};
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28
display/trustedvm-sun-sde-display.dtsi
Normal file
28
display/trustedvm-sun-sde-display.dtsi
Normal file
@@ -0,0 +1,28 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "sun-sde-display-common.dtsi"
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&sde_dsi {
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clocks = <&clock_cpucc 0>,
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<&clock_cpucc 1>,
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<&clock_cpucc 2>,
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<&clock_cpucc 3>;
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clock-names = "pll_byte_clk0", "pll_dsi_clk0",
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"pll_byte_clk1", "pll_dsi_clk1";
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};
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&sde_dsi1 {
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clocks = <&clock_cpucc 0>,
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<&clock_cpucc 1>,
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<&clock_cpucc 2>,
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<&clock_cpucc 3>;
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clock-names = "pll_byte_clk0", "pll_dsi_clk0",
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"pll_byte_clk1", "pll_dsi_clk1";
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};
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&mdss_mdp {
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connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>;
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};
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82
display/trustedvm-sun-sde.dtsi
Normal file
82
display/trustedvm-sun-sde.dtsi
Normal file
@@ -0,0 +1,82 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,dispcc-sun.h>
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include "sun-sde-common.dtsi"
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&soc {
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/* dummy display clock provider */
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clock_cpucc: qcom,cpucc {
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compatible = "qcom,dummycc";
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clock-output-names = "cpucc_clocks";
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#clock-cells = <1>;
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};
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smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
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compatible = "qcom,smmu_sde_unsec";
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iommus = <&apps_smmu 0x804 0x2>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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dma-coherent;
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};
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};
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&mdss_mdp {
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reg = <0x0ae00000 0x93800>,
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<0x0aeb0000 0x2008>,
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<0x0af80000 0x7000>,
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<0x0ae44000 0x02c>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"regdma_phys",
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"sid_phys";
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qcom,sde-vm-exclude-reg-names = "sid_phys";
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qcom,sde-hw-version =<0xC0000000>;
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clocks = <&clock_cpucc GCC_DISP_AHB_CLK>,
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<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
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<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
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<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
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<&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
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<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
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clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk",
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"core_clk", "vsync_clk", "lut_clk";
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qcom,sde-trusted-vm-env;
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};
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&mdss_dsi0 {
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clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
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<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
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<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk";
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};
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&mdss_dsi1 {
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clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
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<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
};
|
||||
|
||||
&mdss_dsi_phy0 {
|
||||
qcom,dsi-pll-in-trusted-vm;
|
||||
};
|
||||
|
||||
&mdss_dsi_phy1 {
|
||||
qcom,dsi-pll-in-trusted-vm;
|
||||
};
|
||||
Reference in New Issue
Block a user