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ARM: dts: msm: Add trustedvm device tree files for Sun target

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Add the trusted VM devicetree nodes for Sun target.

Change-Id: I393576e742d0c793d26558e64a3f39102c1de032
Signed-off-by: Ramkumar Radhakrishnan <quic_rradhakr@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This commit is contained in:
Ramkumar Radhakrishnan
2023-11-22 02:14:39 -08:00
committed by Rui Chen
parent a5e286170d
commit 7d485131a1
7 changed files with 361 additions and 0 deletions
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5
Kbuild
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@@ -1,3 +1,4 @@
ifneq ($(CONFIG_ARCH_QTI_VM), y)
dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
display/sun-sde-display-cdp-overlay.dtbo \ display/sun-sde-display-cdp-overlay.dtbo \
display/sun-sde-display-mtp-overlay.dtbo \ display/sun-sde-display-mtp-overlay.dtbo \
@@ -14,6 +15,10 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
display/sun-sde-display-mtp-nfc-overlay.dtbo \ display/sun-sde-display-mtp-nfc-overlay.dtbo \
display/sun-sde-display-cdp-v8-overlay.dtbo \ display/sun-sde-display-cdp-v8-overlay.dtbo \
display/sun-sde-display-mtp-v8-overlay.dtbo display/sun-sde-display-mtp-v8-overlay.dtbo
else
dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \
display/trustedvm-sun-sde-display-mtp-overlay.dtbo
endif
always-y := $(dtb-y) $(dtbo-y) always-y := $(dtb-y) $(dtbo-y)
subdir-y := $(dts-dirs) subdir-y := $(dts-dirs)

17
display/trustedvm-sun-sde-display-cdp-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "trustedvm-sun-sde.dtsi"
#include "trustedvm-sun-sde-display-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM";
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,board-id = <0x10001 0>;
};

143
display/trustedvm-sun-sde-display-cdp.dtsi Normal file
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@@ -0,0 +1,143 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "trustedvm-sun-sde-display.dtsi"
&dsi_vtdr6130_amoled_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
};
&dsi_vtdr6130_amoled_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
};
&dsi_vtdr6130_amoled_120hz_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_120hz_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sim_panel_au {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sharp_4k_dsc_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
};
&dsi_sharp_4k_dsc_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
};
&dsi_sim_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_vid {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_375_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_10b_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_dual_sim_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
};
&dsi_dual_sim_dsc_375_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_sec_hd_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
};

17
display/trustedvm-sun-sde-display-mtp-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "trustedvm-sun-sde.dtsi"
#include "trustedvm-sun-sde-display-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM";
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,board-id = <0x10008 0>;
};

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display/trustedvm-sun-sde-display-mtp.dtsi Normal file
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@@ -0,0 +1,69 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "trustedvm-sun-sde-display.dtsi"
&dsi_nt37801_amoled_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sim_panel_au {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sim_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_vid {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_375_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_10b_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_dual_sim_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
};
&dsi_dual_sim_dsc_375_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_sec_hd_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
};

28
display/trustedvm-sun-sde-display.dtsi Normal file
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@@ -0,0 +1,28 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-sde-display-common.dtsi"
&sde_dsi {
clocks = <&clock_cpucc 0>,
<&clock_cpucc 1>,
<&clock_cpucc 2>,
<&clock_cpucc 3>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1";
};
&sde_dsi1 {
clocks = <&clock_cpucc 0>,
<&clock_cpucc 1>,
<&clock_cpucc 2>,
<&clock_cpucc 3>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1";
};
&mdss_mdp {
connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>;
};

82
display/trustedvm-sun-sde.dtsi Normal file
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@@ -0,0 +1,82 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,dispcc-sun.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include "sun-sde-common.dtsi"
&soc {
/* dummy display clock provider */
clock_cpucc: qcom,cpucc {
compatible = "qcom,dummycc";
clock-output-names = "cpucc_clocks";
#clock-cells = <1>;
};
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
compatible = "qcom,smmu_sde_unsec";
iommus = <&apps_smmu 0x804 0x2>;
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
qcom,iommu-faults = "non-fatal";
dma-coherent;
};
};
&mdss_mdp {
reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>,
<0x0af80000 0x7000>,
<0x0ae44000 0x02c>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"sid_phys";
qcom,sde-vm-exclude-reg-names = "sid_phys";
qcom,sde-hw-version =<0xC0000000>;
clocks = <&clock_cpucc GCC_DISP_AHB_CLK>,
<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk",
"core_clk", "vsync_clk", "lut_clk";
qcom,sde-trusted-vm-env;
};
&mdss_dsi0 {
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi1 {
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi_phy0 {
qcom,dsi-pll-in-trusted-vm;
};
&mdss_dsi_phy1 {
qcom,dsi-pll-in-trusted-vm;
};