From a3a111ed9574de2c833252e46c7bb84ef6592816 Mon Sep 17 00:00:00 2001
From: Vivek Pernamitta <quic_vpernami@quicinc.com>
Date: Thu, 16 Jan 2025 11:33:09 +0530
Subject: [PATCH] ARM: dts: msm: Increase pipe clock toggles during L1SS entry

Increase the number of pipe clock toggles that will occur after
phystatus goes high at the output of the PHY during L1SS/P2 entry
in PCS_PCIE_POWER_STATE_CONFIG6 register, so that if the phy and
controller goes out of sync this may help us. The number of pipe
clock toggles is equal to (4*value)+1.

Change-Id: I7a31882f18879ef990825aa2d978fc7f39233472
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 qcom/sun-pcie.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/qcom/sun-pcie.dtsi b/qcom/sun-pcie.dtsi
index c46df45c..82952a8e 100644
--- a/qcom/sun-pcie.dtsi
+++ b/qcom/sun-pcie.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/clock/qcom,gcc-sun.h>
@@ -214,6 +214,7 @@
 				0x0814 0x07 0x0
 				0x0820 0xc1 0x0
 				0x0894 0x00 0x0
+				0x08f8 0x1f 0x0
 				0x05d0 0x8c 0x0
 				0x0568 0x17 0x0
 				0x0570 0x2e 0x0