diff --git a/qcom/tuna-pinctrl.dtsi b/qcom/tuna-pinctrl.dtsi
index 83a10696..ad6406c2 100644
--- a/qcom/tuna-pinctrl.dtsi
+++ b/qcom/tuna-pinctrl.dtsi
@@ -4,6 +4,714 @@
  */
 
 &tlmm {
+	qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+		qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active {
+			mux {
+				pins = "gpio52";
+				function = "qup1_se0_l0";
+			};
+
+			config {
+				pins = "gpio52";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active {
+			mux {
+				pins = "gpio53";
+				function = "qup1_se0_l1";
+			};
+
+			config {
+				pins = "gpio53";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+			mux {
+				pins = "gpio52", "gpio53";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio52", "gpio53";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+		qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active {
+			mux {
+				pins = "gpio52";
+				function = "qup1_se0_l0";
+			};
+
+			config {
+				pins = "gpio52";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active {
+			mux {
+				pins = "gpio53";
+				function = "qup1_se0_l1";
+			};
+
+			config {
+				pins = "gpio53";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active {
+			mux {
+				pins = "gpio54";
+				function = "qup1_se0_l2";
+			};
+
+			config {
+				pins = "gpio54";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active {
+			mux {
+				pins = "gpio55";
+				function = "qup1_se0_l3";
+			};
+
+			config {
+				pins = "gpio55";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+			mux {
+				pins = "gpio52", "gpio53",
+					"gpio54", "gpio55";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio52", "gpio53",
+					"gpio54", "gpio55";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
+		qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active {
+			mux {
+				pins = "gpio4";
+				function = "qup1_se1_l0";
+			};
+
+			config {
+				pins = "gpio4";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active {
+			mux {
+				pins = "gpio5";
+				function = "qup1_se1_l1";
+			};
+
+			config {
+				pins = "gpio5";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se1_spi_pins: qupv3_se1_spi_pins {
+		qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active {
+			mux {
+				pins = "gpio4";
+				function = "qup1_se1_l0";
+			};
+
+			config {
+				pins = "gpio4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active {
+			mux {
+				pins = "gpio5";
+				function = "qup1_se1_l1";
+			};
+
+			config {
+				pins = "gpio5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active {
+			mux {
+				pins = "gpio6";
+				function = "qup1_se1_l2";
+			};
+
+			config {
+				pins = "gpio6";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active {
+			mux {
+				pins = "gpio7";
+				function = "qup1_se1_l3";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
+			mux {
+				pins = "gpio4", "gpio5",
+					"gpio6", "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5",
+					"gpio6", "gpio7";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+		qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active {
+			mux {
+				pins = "gpio8";
+				function = "qup1_se2_l0";
+			};
+
+			config {
+				pins = "gpio8";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active {
+			mux {
+				pins = "gpio9";
+				function = "qup1_se2_l1";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+			mux {
+				pins = "gpio8", "gpio9";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio8", "gpio9";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+		qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active {
+			mux {
+				pins = "gpio8";
+				function = "qup1_se2_l0";
+			};
+
+			config {
+				pins = "gpio8";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active {
+			mux {
+				pins = "gpio9";
+				function = "qup1_se2_l1";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active {
+			mux {
+				pins = "gpio10";
+				function = "qup1_se2_l2";
+			};
+
+			config {
+				pins = "gpio10";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active {
+			mux {
+				pins = "gpio11";
+				function = "qup1_se2_l3";
+			};
+
+			config {
+				pins = "gpio11";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+			mux {
+				pins = "gpio8", "gpio9",
+					"gpio10", "gpio11";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio8", "gpio9",
+					"gpio10", "gpio11";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
+		qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active {
+			mux {
+				pins = "gpio60";
+				function = "qup1_se3_l0";
+			};
+
+			config {
+				pins = "gpio60";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active {
+			mux {
+				pins = "gpio61";
+				function = "qup1_se3_l1";
+			};
+
+			config {
+				pins = "gpio61";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
+			mux {
+				pins = "gpio60", "gpio61";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio60", "gpio61";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
+		qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active {
+			mux {
+				pins = "gpio16";
+				function = "qup1_se4_l0";
+			};
+
+			config {
+				pins = "gpio16";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active {
+			mux {
+				pins = "gpio17";
+				function = "qup1_se4_l1";
+			};
+
+			config {
+				pins = "gpio17";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
+			mux {
+				pins = "gpio16", "gpio17";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio16", "gpio17";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se4_spi_pins: qupv3_se4_spi_pins {
+		qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active {
+			mux {
+				pins = "gpio16";
+				function = "qup1_se4_l0";
+			};
+
+			config {
+				pins = "gpio16";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active {
+			mux {
+				pins = "gpio17";
+				function = "qup1_se4_l1";
+			};
+
+			config {
+				pins = "gpio17";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active {
+			mux {
+				pins = "gpio18";
+				function = "qup1_se4_l2";
+			};
+
+			config {
+				pins = "gpio18";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active {
+			mux {
+				pins = "gpio19";
+				function = "qup1_se4_l3";
+			};
+
+			config {
+				pins = "gpio19";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
+			mux {
+				pins = "gpio16", "gpio17",
+					"gpio18", "gpio19";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio16", "gpio17",
+					"gpio18", "gpio19";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
+		qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active {
+			mux {
+				pins = "gpio12";
+				function = "qup1_se5_l0";
+			};
+
+			config {
+				pins = "gpio12";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active {
+			mux {
+				pins = "gpio13";
+				function = "qup1_se5_l1";
+			};
+
+			config {
+				pins = "gpio13";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
+			mux {
+				pins = "gpio12", "gpio13";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio12", "gpio13";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se5_spi_pins: qupv3_se5_spi_pins {
+		qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active {
+			mux {
+				pins = "gpio12";
+				function = "qup1_se5_l0";
+			};
+
+			config {
+				pins = "gpio12";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active {
+			mux {
+				pins = "gpio13";
+				function = "qup1_se5_l1";
+			};
+
+			config {
+				pins = "gpio13";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active {
+			mux {
+				pins = "gpio14";
+				function = "qup1_se5_l2";
+			};
+
+			config {
+				pins = "gpio14";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active {
+			mux {
+				pins = "gpio15";
+				function = "qup1_se5_l3";
+			};
+
+			config {
+				pins = "gpio15";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
+			mux {
+				pins = "gpio12", "gpio13",
+					"gpio14", "gpio15";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio12", "gpio13",
+					"gpio14", "gpio15";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
+		qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active {
+			mux {
+				pins = "gpio24";
+				function = "qup1_se6_l0";
+			};
+
+			config {
+				pins = "gpio24";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active {
+			mux {
+				pins = "gpio25";
+				function = "qup1_se6_l1";
+			};
+
+			config {
+				pins = "gpio25";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
+			mux {
+				pins = "gpio24", "gpio25";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio24", "gpio25";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se6_spi_pins: qupv3_se6_spi_pins {
+		qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active {
+			mux {
+				pins = "gpio24";
+				function = "qup1_se6_l0";
+			};
+
+			config {
+				pins = "gpio24";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active {
+			mux {
+				pins = "gpio25";
+				function = "qup1_se6_l1";
+			};
+
+			config {
+				pins = "gpio25";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active {
+			mux {
+				pins = "gpio26";
+				function = "qup1_se6_l2";
+			};
+
+			config {
+				pins = "gpio26";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active {
+			mux {
+				pins = "gpio27";
+				function = "qup1_se6_l3";
+			};
+
+			config {
+				pins = "gpio27";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
+			mux {
+				pins = "gpio24", "gpio25",
+					"gpio26", "gpio27";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio24", "gpio25",
+					"gpio26", "gpio27";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
 	qupv3_se7_2uart_pins: qupv3_se7_2uart_pins {
 		qupv3_se7_2uart_tx_active: qupv3_se7_2uart_tx_active {
 			mux {
@@ -44,4 +752,832 @@
 			};
 		};
 	};
+
+	qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
+		qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active {
+			mux {
+				pins = "gpio0";
+				function = "qup2_se0_l0";
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active {
+			mux {
+				pins = "gpio1";
+				function = "qup2_se0_l1";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
+			mux {
+				pins = "gpio0", "gpio1";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0", "gpio1";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se8_spi_pins: qupv3_se8_spi_pins {
+		qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active {
+			mux {
+				pins = "gpio0";
+				function = "qup2_se0_l0";
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active {
+			mux {
+				pins = "gpio1";
+				function = "qup2_se0_l1";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active {
+			mux {
+				pins = "gpio2";
+				function = "qup2_se0_l2";
+			};
+
+			config {
+				pins = "gpio2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active {
+			mux {
+				pins = "gpio3";
+				function = "qup2_se0_l3";
+			};
+
+			config {
+				pins = "gpio3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
+			mux {
+				pins = "gpio0", "gpio1",
+					"gpio2", "gpio3";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0", "gpio1",
+					"gpio2", "gpio3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
+		qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active {
+			mux {
+				pins = "gpio179";
+				function = "qup2_se1_l0";
+			};
+
+			config {
+				pins = "gpio179";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active {
+			mux {
+				pins = "gpio180";
+				function = "qup2_se1_l1";
+			};
+
+			config {
+				pins = "gpio180";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
+			mux {
+				pins = "gpio179", "gpio180";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio179", "gpio180";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
+		qupv3_se10_i2c_sda_active: qupv3_se10_i2c_sda_active {
+			mux {
+				pins = "gpio56";
+				function = "qup2_se2_l0";
+			};
+
+			config {
+				pins = "gpio56";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se10_i2c_scl_active: qupv3_se10_i2c_scl_active {
+			mux {
+				pins = "gpio57";
+				function = "qup2_se2_l1";
+			};
+
+			config {
+				pins = "gpio57";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
+			mux {
+				pins = "gpio56", "gpio57";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio56", "gpio57";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se10_spi_pins: qupv3_se10_spi_pins {
+		qupv3_se10_spi_miso_active: qupv3_se10_spi_miso_active {
+			mux {
+				pins = "gpio56";
+				function = "qup2_se2_l0";
+			};
+
+			config {
+				pins = "gpio56";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se10_spi_mosi_active: qupv3_se10_spi_mosi_active {
+			mux {
+				pins = "gpio57";
+				function = "qup2_se2_l1";
+			};
+
+			config {
+				pins = "gpio57";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se10_spi_clk_active: qupv3_se10_spi_clk_active {
+			mux {
+				pins = "gpio58";
+				function = "qup2_se2_l2";
+			};
+
+			config {
+				pins = "gpio58";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se10_spi_cs_active: qupv3_se10_spi_cs_active {
+			mux {
+				pins = "gpio59";
+				function = "qup2_se2_l3";
+			};
+
+			config {
+				pins = "gpio59";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
+			mux {
+				pins = "gpio56", "gpio57",
+					"gpio58", "gpio59";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio56", "gpio57",
+					"gpio58", "gpio59";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
+		qupv3_se11_i2c_sda_active: qupv3_se11_i2c_sda_active {
+			mux {
+				pins = "gpio36";
+				function = "qup2_se3_l0";
+			};
+
+			config {
+				pins = "gpio36";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se11_i2c_scl_active: qupv3_se11_i2c_scl_active {
+			mux {
+				pins = "gpio37";
+				function = "qup2_se3_l1";
+			};
+
+			config {
+				pins = "gpio37";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
+			mux {
+				pins = "gpio36", "gpio37";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio36", "gpio37";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se11_spi_pins: qupv3_se11_spi_pins {
+		qupv3_se11_spi_miso_active: qupv3_se11_spi_miso_active {
+			mux {
+				pins = "gpio36";
+				function = "qup2_se3_l0";
+			};
+
+			config {
+				pins = "gpio36";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se11_spi_mosi_active: qupv3_se11_spi_mosi_active {
+			mux {
+				pins = "gpio37";
+				function = "qup2_se3_l1";
+			};
+
+			config {
+				pins = "gpio37";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se11_spi_clk_active: qupv3_se11_spi_clk_active {
+			mux {
+				pins = "gpio38";
+				function = "qup2_se3_l2";
+			};
+
+			config {
+				pins = "gpio38";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se11_spi_cs_active: qupv3_se11_spi_cs_active {
+			mux {
+				pins = "gpio39";
+				function = "qup2_se3_l3";
+			};
+
+			config {
+				pins = "gpio39";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
+			mux {
+				pins = "gpio36", "gpio37",
+					"gpio38", "gpio39";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio36", "gpio37",
+					"gpio38", "gpio39";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
+		qupv3_se12_i2c_sda_active: qupv3_se12_i2c_sda_active {
+			mux {
+				pins = "gpio32";
+				function = "qup2_se4_l0";
+			};
+
+			config {
+				pins = "gpio32";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se12_i2c_scl_active: qupv3_se12_i2c_scl_active {
+			mux {
+				pins = "gpio33";
+				function = "qup2_se4_l1";
+			};
+
+			config {
+				pins = "gpio33";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
+			mux {
+				pins = "gpio32", "gpio33";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio32", "gpio33";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se12_spi_pins: qupv3_se12_spi_pins {
+		qupv3_se12_spi_miso_active: qupv3_se12_spi_miso_active {
+			mux {
+				pins = "gpio32";
+				function = "qup2_se4_l0";
+			};
+
+			config {
+				pins = "gpio32";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se12_spi_mosi_active: qupv3_se12_spi_mosi_active {
+			mux {
+				pins = "gpio33";
+				function = "qup2_se4_l1";
+			};
+
+			config {
+				pins = "gpio33";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se12_spi_clk_active: qupv3_se12_spi_clk_active {
+			mux {
+				pins = "gpio34";
+				function = "qup2_se4_l2";
+			};
+
+			config {
+				pins = "gpio34";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se12_spi_cs_active: qupv3_se12_spi_cs_active {
+			mux {
+				pins = "gpio35";
+				function = "qup2_se4_l3";
+			};
+
+			config {
+				pins = "gpio35";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
+			mux {
+				pins = "gpio32", "gpio33",
+					"gpio34", "gpio35";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio32", "gpio33",
+					"gpio34", "gpio35";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
+		qupv3_se13_i2c_sda_active: qupv3_se13_i2c_sda_active {
+			mux {
+				pins = "gpio20";
+				function = "qup2_se5_l0";
+			};
+
+			config {
+				pins = "gpio20";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se13_i2c_scl_active: qupv3_se13_i2c_scl_active {
+			mux {
+				pins = "gpio21";
+				function = "qup2_se5_l1";
+			};
+
+			config {
+				pins = "gpio21";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
+			mux {
+				pins = "gpio20", "gpio21";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio20", "gpio21";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se13_spi_pins: qupv3_se13_spi_pins {
+		qupv3_se13_spi_miso_active: qupv3_se13_spi_miso_active {
+			mux {
+				pins = "gpio20";
+				function = "qup2_se5_l0";
+			};
+
+			config {
+				pins = "gpio20";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_spi_mosi_active: qupv3_se13_spi_mosi_active {
+			mux {
+				pins = "gpio21";
+				function = "qup2_se5_l1";
+			};
+
+			config {
+				pins = "gpio21";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_spi_clk_active: qupv3_se13_spi_clk_active {
+			mux {
+				pins = "gpio22";
+				function = "qup2_se5_l2";
+			};
+
+			config {
+				pins = "gpio22";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_spi_cs_active: qupv3_se13_spi_cs_active {
+			mux {
+				pins = "gpio23";
+				function = "qup2_se5_l3";
+			};
+
+			config {
+				pins = "gpio23";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
+			mux {
+				pins = "gpio20", "gpio21",
+					"gpio22", "gpio23";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio20", "gpio21",
+					"gpio22", "gpio23";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se14_4uart_pins: qupv3_se14_4uart_pins {
+		qupv3_se14_default_cts: qupv3_se14_default_cts {
+			mux {
+				pins = "gpio40";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio40";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se14_default_rts: qupv3_se14_default_rts {
+			mux {
+				pins = "gpio41";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio41";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se14_default_tx: qupv3_se14_default_tx {
+			mux {
+				pins = "gpio42";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio42";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se14_default_rx: qupv3_se14_default_rx {
+			mux {
+				pins = "gpio43";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio43";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se14_cts: qupv3_se14_cts {
+			mux {
+				pins = "gpio40";
+				function = "qup2_se6_l0";
+			};
+
+			config {
+				pins = "gpio40";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se14_rts: qupv3_se14_rts {
+			mux {
+				pins = "gpio41";
+				function = "qup2_se6_l1";
+			};
+
+			config {
+				pins = "gpio41";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se14_tx: qupv3_se14_tx {
+			mux {
+				pins = "gpio42";
+				function = "qup2_se6_l2";
+			};
+
+			config {
+				pins = "gpio42";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se14_rx_active: qupv3_se14_rx_active {
+			mux {
+				pins = "gpio43";
+				function = "qup2_se6_l3";
+			};
+
+			config {
+				pins = "gpio43";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		/* RX to be in gpio mode for sleep config */
+		qupv3_se14_rx_wake: qupv3_se14_rx_wake {
+			mux {
+				pins = "gpio43";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio43";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
+		qupv3_se15_i2c_sda_active: qupv3_se15_i2c_sda_active {
+			mux {
+				pins = "gpio44";
+				function = "qup2_se7_l0";
+			};
+
+			config {
+				pins = "gpio44";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se15_i2c_scl_active: qupv3_se15_i2c_scl_active {
+			mux {
+				pins = "gpio45";
+				function = "qup2_se7_l1";
+			};
+
+			config {
+				pins = "gpio45";
+				drive-strength = <2>;
+				bias-pull-up;
+				qcom,i2c_pull;
+			};
+		};
+
+		qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
+			mux {
+				pins = "gpio44", "gpio45";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio44", "gpio45";
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	qupv3_se15_spi_pins: qupv3_se15_spi_pins {
+		qupv3_se15_spi_miso_active: qupv3_se15_spi_miso_active {
+			mux {
+				pins = "gpio44";
+				function = "qup2_se7_l0";
+			};
+
+			config {
+				pins = "gpio44";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se15_spi_mosi_active: qupv3_se15_spi_mosi_active {
+			mux {
+				pins = "gpio45";
+				function = "qup2_se7_l1";
+			};
+
+			config {
+				pins = "gpio45";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se15_spi_clk_active: qupv3_se15_spi_clk_active {
+			mux {
+				pins = "gpio46";
+				function = "qup2_se7_l2";
+			};
+
+			config {
+				pins = "gpio46";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se15_spi_cs_active: qupv3_se15_spi_cs_active {
+			mux {
+				pins = "gpio47";
+				function = "qup2_se7_l3";
+			};
+
+			config {
+				pins = "gpio47";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
+			mux {
+				pins = "gpio44", "gpio45",
+					"gpio46", "gpio47";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio44", "gpio45",
+					"gpio46", "gpio47";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
 };
diff --git a/qcom/tuna-qupv3.dtsi b/qcom/tuna-qupv3.dtsi
index f7100943..8e7e3077 100644
--- a/qcom/tuna-qupv3.dtsi
+++ b/qcom/tuna-qupv3.dtsi
@@ -4,7 +4,62 @@
  */
 
 &soc {
-	/* QUPv3_1 Wrapper Instance */
+	/* QUPv3 SE Instances
+	 * Qup1 0: SE 0
+	 * Qup1 1: SE 1
+	 * Qup1 2: SE 2
+	 * Qup1 3: SE 3
+	 * Qup1 4: SE 4
+	 * Qup1 5: SE 5
+	 * Qup1 6: SE 6
+	 * Qup1 7: SE 7
+	 * Qup2 0: SE 8
+	 * Qup2 1: SE 9
+	 * Qup2 2: SE 10
+	 * Qup2 3: SE 11
+	 * Qup2 4: SE 12
+	 * Qup2 5: SE 13
+	 * Qup2 6: SE 14
+	 * Qup2 7: SE 15
+	 */
+
+	qup1_gpi_iommu_region: qup1_gpi_iommu_region {
+		iommu-addresses = <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xffe00000>;
+	};
+
+	/* GPI Instance */
+	gpi_dma1: qcom,gpi-dma@a00000 {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0xa00000 0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0xb6 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0x1f>;
+		qcom,ev-factor = <1>;
+		memory-region = <&qup1_gpi_iommu_region>;
+		qcom,gpi-ee-offset = <0x10000>;
+		dma-coherent;
+		status = "ok";
+	};
+
+	qup1_se_iommu_region: qup1_se_iommu_region {
+		iommu-addresses = <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>;
+	};
+
+	/* QUPv3_1 wrapper instance */
 	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
 		compatible = "qcom,geni-se-qup";
 		reg = <0xac0000 0x2000>;
@@ -13,9 +68,319 @@
 		clock-names = "m-ahb", "s-ahb";
 		clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		iommus = <&apps_smmu 0xa3 0x0>;
+		memory-region = <&qup1_se_iommu_region>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
 		ranges;
 		status = "ok";
 
+		qupv3_se0_i2c: i2c@a80000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa80000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+			dmas = <&gpi_dma1 0 0 3 64 0>,
+				<&gpi_dma1 1 0 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se0_spi: spi@a80000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa80000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
+				<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se0_spi_sleep>;
+			dmas = <&gpi_dma1 0 0 1 64 0>,
+				<&gpi_dma1 1 0 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se1_i2c: i2c@a84000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa84000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+			dmas = <&gpi_dma1 0 1 3 64 0>,
+				<&gpi_dma1 1 1 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se1_spi: spi@a84000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa84000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
+				<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se1_spi_sleep>;
+			dmas = <&gpi_dma1 0 1 1 64 0>,
+				<&gpi_dma1 1 1 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se2_i2c: i2c@a88000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa88000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+			dmas = <&gpi_dma1 0 2 3 64 0>,
+				<&gpi_dma1 1 2 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se2_spi: spi@a88000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa88000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
+				<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se2_spi_sleep>;
+			dmas = <&gpi_dma1 0 2 1 64 0>,
+				<&gpi_dma1 1 2 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se3_i2c: i2c@a8c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa8c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se3_i2c_sleep>;
+			dmas = <&gpi_dma1 0 3 3 64 0>,
+				<&gpi_dma1 1 3 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se4_i2c: i2c@a90000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa90000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+			dmas = <&gpi_dma1 0 4 3 64 0>,
+				<&gpi_dma1 1 4 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se4_spi: spi@a90000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa90000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
+				<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se4_spi_sleep>;
+			dmas = <&gpi_dma1 0 4 1 64 0>,
+				<&gpi_dma1 1 4 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se5_i2c: i2c@a94000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa94000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+			dmas = <&gpi_dma1 0 5 3 1024 0>,
+				<&gpi_dma1 1 5 3 1024 0>;
+			dma-names = "tx", "rx";
+			qcom,shared;
+			status = "disabled";
+		};
+
+		qupv3_se5_spi: spi@a94000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa94000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
+				<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se5_spi_sleep>;
+			dmas = <&gpi_dma1 0 5 1 64 0>,
+				<&gpi_dma1 1 5 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se6_i2c: i2c@a98000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa98000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+			dmas = <&gpi_dma1 0 6 3 64 0>,
+				<&gpi_dma1 1 6 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se6_spi: spi@a98000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa98000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
+				<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se6_spi_sleep>;
+			dmas = <&gpi_dma1 0 6 1 64 0>,
+				<&gpi_dma1 1 6 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
 		/* Debug UART Instance */
 		qupv3_se7_2uart: qcom,qup_uart@a9c000 {
 			compatible = "qcom,geni-debug-uart";
@@ -30,4 +395,389 @@
 			status = "disabled";
 		};
 	};
+	qup2_gpi_iommu_region: qup2_gpi_iommu_region {
+		iommu-addresses = <&gpi_dma2 0x0 0x100000>, <&gpi_dma2 0x200000 0xffe00000>;
+	};
+
+	/* GPI Instance */
+	gpi_dma2: qcom,gpi-dma@800000 {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x800000 0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0x436 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0x1f>;
+		qcom,ev-factor = <1>;
+		memory-region = <&qup2_gpi_iommu_region>;
+		qcom,gpi-ee-offset = <0x10000>;
+		dma-coherent;
+		status = "ok";
+	};
+
+	qup2_se_iommu_region: qup2_se_iommu_region {
+		iommu-addresses = <&qupv3_2 0x0 0x40000000>, <&qupv3_2 0x50000000 0xb0000000>;
+	};
+
+	/* QUPv3_2 wrapper instance */
+	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x8c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x423 0x0>;
+		memory-region = <&qup2_se_iommu_region>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+		ranges;
+		status = "ok";
+
+		qupv3_se8_i2c: i2c@880000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x880000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se8_i2c_sleep>;
+			dmas = <&gpi_dma2 0 0 3 64 0>,
+				<&gpi_dma2 1 0 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se8_spi: spi@880000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x880000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
+				<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se8_spi_sleep>;
+			dmas = <&gpi_dma2 0 0 1 64 0>,
+				<&gpi_dma2 1 0 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se9_i2c: i2c@884000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x884000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se9_i2c_sleep>;
+			dmas = <&gpi_dma2 0 1 3 64 0>,
+				<&gpi_dma2 1 1 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se10_i2c: i2c@888000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x888000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se10_i2c_sda_active>, <&qupv3_se10_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se10_i2c_sleep>;
+			dmas = <&gpi_dma2 0 2 3 64 0>,
+				<&gpi_dma2 1 2 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se10_spi: spi@888000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x888000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se10_spi_mosi_active>, <&qupv3_se10_spi_miso_active>,
+				<&qupv3_se10_spi_clk_active>, <&qupv3_se10_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se10_spi_sleep>;
+			dmas = <&gpi_dma2 0 2 1 64 0>,
+				<&gpi_dma2 1 2 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se11_i2c: i2c@88c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x88c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se11_i2c_sda_active>, <&qupv3_se11_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se11_i2c_sleep>;
+			dmas = <&gpi_dma2 0 3 3 64 0>,
+				<&gpi_dma2 1 3 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se11_spi: spi@88c000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x88c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se11_spi_mosi_active>, <&qupv3_se11_spi_miso_active>,
+				<&qupv3_se11_spi_clk_active>, <&qupv3_se11_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se11_spi_sleep>;
+			dmas = <&gpi_dma2 0 3 1 64 0>,
+				<&gpi_dma2 1 3 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se12_i2c: i2c@890000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x890000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se12_i2c_sda_active>, <&qupv3_se12_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se12_i2c_sleep>;
+			dmas = <&gpi_dma2 0 4 3 64 0>,
+				<&gpi_dma2 1 4 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se12_spi: spi@890000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x890000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se12_spi_mosi_active>, <&qupv3_se12_spi_miso_active>,
+				<&qupv3_se12_spi_clk_active>, <&qupv3_se12_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se12_spi_sleep>;
+			dmas = <&gpi_dma2 0 4 1 64 0>,
+				<&gpi_dma2 1 4 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se13_i2c: i2c@894000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x894000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se13_i2c_sda_active>, <&qupv3_se13_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se13_i2c_sleep>;
+			dmas = <&gpi_dma2 0 5 3 64 0>,
+				<&gpi_dma2 1 5 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se13_spi: spi@894000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x894000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se13_spi_mosi_active>, <&qupv3_se13_spi_miso_active>,
+				<&qupv3_se13_spi_clk_active>, <&qupv3_se13_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se13_spi_sleep>;
+			dmas = <&gpi_dma2 0 5 1 64 0>,
+				<&gpi_dma2 1 5 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		/* HS UART Instance */
+		qupv3_se14_4uart: qcom,qup_uart@898000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x898000 0x4000>;
+			reg-names = "se_phys";
+			interrupts-extended = <&intc GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+					<&tlmm 43 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>,
+			<&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>;
+			pinctrl-1 = <&qupv3_se14_cts>, <&qupv3_se14_rts>,
+			<&qupv3_se14_tx>, <&qupv3_se14_rx_active>;
+			pinctrl-2 = <&qupv3_se14_cts>, <&qupv3_se14_rts>,
+			<&qupv3_se14_tx>, <&qupv3_se14_rx_wake>;
+			pinctrl-3 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>,
+			<&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>;
+			qcom,wakeup-byte = <0xFD>;
+			qcom,suspend-ignore-children;
+			status = "disabled";
+		};
+
+		qupv3_se15_i2c: i2c@89c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x89c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se15_i2c_sleep>;
+			dmas = <&gpi_dma2 0 7 3 64 0>,
+				<&gpi_dma2 1 7 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se15_spi: spi@89c000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x89c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>,
+				<&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se15_spi_sleep>;
+			dmas = <&gpi_dma2 0 7 1 64 0>,
+				<&gpi_dma2 1 7 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+	};
 };
diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi
index 620dacd7..d8680303 100644
--- a/qcom/tuna.dtsi
+++ b/qcom/tuna.dtsi
@@ -50,6 +50,33 @@
 	aliases {
 		serial0 = &qupv3_se7_2uart;
 		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
+		hsuart0 = &qupv3_se14_4uart;
+		i2c0 = &qupv3_se0_i2c;
+		i2c1 = &qupv3_se1_i2c;
+		i2c2 = &qupv3_se2_i2c;
+		i2c3 = &qupv3_se3_i2c;
+		i2c4 = &qupv3_se4_i2c;
+		i2c5 = &qupv3_se5_i2c;
+		i2c6 = &qupv3_se6_i2c;
+		i2c8 = &qupv3_se8_i2c;
+		i2c9 = &qupv3_se9_i2c;
+		i2c10 = &qupv3_se10_i2c;
+		i2c11 = &qupv3_se11_i2c;
+		i2c12 = &qupv3_se12_i2c;
+		i2c13 = &qupv3_se13_i2c;
+		i2c15 = &qupv3_se15_i2c;
+		spi0 = &qupv3_se0_spi;
+		spi1 = &qupv3_se1_spi;
+		spi2 = &qupv3_se2_spi;
+		spi4 = &qupv3_se4_spi;
+		spi5 = &qupv3_se5_spi;
+		spi6 = &qupv3_se6_spi;
+		spi8 = &qupv3_se8_spi;
+		spi10 = &qupv3_se10_spi;
+		spi11 = &qupv3_se11_spi;
+		spi12 = &qupv3_se12_spi;
+		spi13 = &qupv3_se13_spi;
+		spi15 = &qupv3_se15_spi;
 	};
 
 	cpus {