From 4f215a58daeeebe59759d19948782fb1fe336090 Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Thu, 26 Sep 2024 18:46:23 +0530 Subject: [PATCH 01/12] ARM: dts: msm: add qcom,dsi-select-sec-sync-clocks property Currently, we are using the qcom,dsi-select-sec-clocks property to select the clock source for secondary display when sync mode is enabled. In the use case, when DPU0 is faulty and DPU1 is working, the clock source of the secondary display needs to be changed from _mclk to _clk2. Add a new property called qcom,dsi-select-sec-sync-clocks to specify the clock source of the secondary display when running in sync mode with dual DPU. This way, existing "qcom,dsi-select- sec-clocks" property can be used as clock source for the secondary display when DPU0 is faulty/disabled. Change-Id: I3ced083b6700921549e7036722a73d7a4f1f41e5 Signed-off-by: Ayushi Makhija Signed-off-by: lnxdisplay --- bindings/sde-dsi.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/sde-dsi.yaml b/bindings/sde-dsi.yaml index 6e85620c..ebf4c9b8 100644 --- a/bindings/sde-dsi.yaml +++ b/bindings/sde-dsi.yaml @@ -263,6 +263,10 @@ properties: qcom,dsi-select-sec-clocks: description: Specifies the required clocks to use for secondary panel + qcom,dsi-select-sec-sync-clocks: + description: Specifies the required clocks to use for secondary + panel when sync mode is enabled. + qcom,dsi-display-list: description: Specifies the list of supported displays. $ref: /schemas/types.yaml#/definitions/string-array From 4a86f982acd4fad1673f67aa1809bab7db31ea85 Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Thu, 26 Sep 2024 18:38:31 +0530 Subject: [PATCH 02/12] ARM: dts: msm: update documentation for qcom,mdp Use "qcom,mdp" to specify the list of phandles for all the DPU instances. This will enable a DSI display driver to know all the DPUs present in the system. This can also be used to differentiate single DPU and dual DPU usecases based on number of MDPs enabled. Change-Id: I668c971b4e227d4a0c8fa321ed624bc45a43b163 Signed-off-by: Ayushi Makhija Signed-off-by: lnxdisplay --- bindings/sde-dsi.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/sde-dsi.yaml b/bindings/sde-dsi.yaml index ebf4c9b8..9ff4625e 100644 --- a/bindings/sde-dsi.yaml +++ b/bindings/sde-dsi.yaml @@ -192,7 +192,7 @@ properties: description: Specifies the default panel. qcom,mdp: - description: Specifies the mdp node which can find panel node from this. + description: Specifies the list of phandles to all sde kms device nodes. qcom,demura-panel-id: description: | From 984fda4d7d77fc3b6225cfee7fd06fd0cbda79ea Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Fri, 25 Oct 2024 13:35:06 +0530 Subject: [PATCH 03/12] ARM: dts: msm: add initial dsi display nodes for Kera Add initial dsi display nodes for Kera. Change-Id: I09194c34f8ac1ec6d606879267b1732a72c0cd4e Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 149 ++++++++++++++++++++++++++++++++++ display/kera-sde-display.dtsi | 147 +++++++++++++++++++++++++++++++++ display/kera-sde.dts | 14 ++++ display/kera-sde.dtsi | 58 +++++++++++++ 4 files changed, 368 insertions(+) create mode 100644 display/kera-sde-common.dtsi create mode 100644 display/kera-sde-display.dtsi create mode 100644 display/kera-sde.dts create mode 100644 display/kera-sde.dtsi diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi new file mode 100644 index 00000000..4f0e2247 --- /dev/null +++ b/display/kera-sde-common.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1320000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1320000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae95000 0xa00>, + <0xae95500 0x400>, + <0xae94200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae97000 0xa00>, + <0xae97500 0x400>, + <0xae96200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +}; diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi new file mode 100644 index 00000000..2159dfde --- /dev/null +++ b/display/kera-sde-display.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "kera-sde-display-common.dtsi" + +&soc { +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 2>, + <&mdss_dsi_phy1 3>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L1G>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 2>, + <&mdss_dsi_phy1 3>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L1G>; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; +}; + +&dsi_vtdr6130_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd vid mode*/ + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2 { /* FHD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <540 20 540 20 540 20>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@3 { /* HD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; diff --git a/display/kera-sde.dts b/display/kera-sde.dts new file mode 100644 index 00000000..f6c6ae21 --- /dev/null +++ b/display/kera-sde.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde.dtsi" + +/ { + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi new file mode 100644 index 00000000..38714fa9 --- /dev/null +++ b/display/kera-sde.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "kera-sde-common.dtsi" + +&soc { +}; + +&mdss_mdp { +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; From 4eced6e8c62d19d61ad393199f8b2e8ed221031e Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Mon, 28 Oct 2024 14:07:38 +0530 Subject: [PATCH 04/12] ARM: dts: msm: add initial dp display nodes for Kera target Add initial dp display nodes for Kera target. Change-Id: Ic1b7abe71ae58b414c5d51a10d4b99a3c1e862cb Signed-off-by: Mani Chandana Ballary Kuntumalla Signed-off-by: lnxdisplay --- display/kera-sde.dtsi | 169 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 38714fa9..83cf63be 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -3,11 +3,180 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include +#include #include +#include #include "kera-sde-common.dtsi" &soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp_pll: qcom,dp_pll@88ea000 { + compatible = "qcom,dp-pll-4nm-v1.1"; + #clock-cells = <1>; + }; + + sde_dp: qcom,dp_display@af54000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + status = "disabled"; + + //usb-phy = <&usb_qmp_dp_phy>; + qcom,ext-disp = <&ext_disp>; + usb-controller = <&usb0>; + qcom,altmode-dev = <&altmode 0>; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0x88ea000 0x200>, + <0x88e8000 0x020>, + <0xaee1000 0x034>, + <0xaf57000 0x09c>, + <0xaf09000 0x014>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pll", "usb3_dp_com", "hdcp_physical", + "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&sde_dp_pll 0>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&sde_dp_pll 1>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,dp-pll = <&sde_dp_pll>; + qcom,phy-version = <0x600>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,widebus-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L4B>; + vdda-0p9-supply = <&L7K>; + vdda_usb-0p9-supply = <&L7K>; + //vdd_mx-supply = <&VDD_MXA_LEVEL>; + dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, + <0x11 0x1e 0x1f 0xff>, + <0x16 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, + <0x00 0x0e 0x15 0xff>, + <0x00 0x0e 0xff 0xff>, + <0x02 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, + <0x09 0x19 0x1f 0xff>, + <0x10 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, + <0x02 0x0e 0x16 0xff>, + <0x02 0x11 0xff 0xff>, + <0x04 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1320000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <114000>; + qcom,supply-disable-load = <0>; + }; + + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda_usb-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <2500>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; }; &mdss_mdp { From 9739f4c25ed29a6c9a22b86f77508a8c8d8a3672 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Mon, 23 Sep 2024 17:38:41 +0800 Subject: [PATCH 05/12] ARM: dts: msm: enable 4-3-2 topology for sharp 4k Enable 4-3-2 topology for both cmd and video mode on sharp 4k panel for sun target. Change-Id: I76dca958eea693d495c17320c56922f9a9ffa74b Signed-off-by: Jinfeng Gu Signed-off-by: lnxdisplay --- display/sun-sde-display-common.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index c8c82641..cb197717 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -763,7 +763,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 05 06 02 04 00 12 0a]; - qcom,display-topology = <2 2 2>; + qcom,display-topology = <2 2 2>, + <4 3 2>; qcom,default-topology-index = <0>; }; }; @@ -784,7 +785,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 06 07 02 04 00 15 0b]; - qcom,display-topology = <2 2 2>; + qcom,display-topology = <2 2 2>, + <4 3 2>; qcom,default-topology-index = <0>; }; }; From d83ba874286f3531d5bad1da2d20a964d8d4a4b7 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 24 Oct 2024 18:21:09 +0800 Subject: [PATCH 06/12] ARM: dts: msm: add sharp QHD plus cmd/video mode panel support This change added sharp QHD plus cmd/video mode panel support. Change-Id: Id0420be23cbc583500fe280d410e1a568e03f9a1 Signed-off-by: Jinfeng Gu Signed-off-by: lnxdisplay --- display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi | 211 ++++++++++++++++++ .../dsi-panel-sharp-dsc-qhd-plus-video.dtsi | 204 +++++++++++++++++ 2 files changed, 415 insertions(+) create mode 100644 display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi create mode 100644 display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi new file mode 100644 index 00000000..ff0dfc0f --- /dev/null +++ b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sharp_qhd_plus_dsc_cmd: qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd { + qcom,mdss-dsi-panel-name = "Sharp qhd cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-mdp-transfer-time-us = <7933>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 44 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi new file mode 100644 index 00000000..00a7ea92 --- /dev/null +++ b/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sharp_qhd_plus_dsc_video: qcom,mdss_dsi_sharp_qhd_plus_dsc_video { + qcom,mdss-dsi-panel-name = "Sharp qhd video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; From d0f765f345060fc244944b1150f1a2f940a93d1e Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Wed, 25 Sep 2024 17:02:58 +0800 Subject: [PATCH 07/12] ARM: dts: msm: enable 4-4-2 topology for sharp QHD plus panel This change enabled 4LM and 4DSC topology for sharp QHD plus panel. Change-Id: I3f6c348c6235575c2b14ac73d5ac50c19b1acc1c Signed-off-by: Jinfeng Gu Signed-off-by: lnxdisplay --- display/sun-sde-display-cdp.dtsi | 26 ++++++++++++++++++++++++-- display/sun-sde-display-common.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index b2dd5503..9ec15fff 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -236,6 +236,24 @@ qcom,platform-bklight-en-gpio = <&tlmm 100 0>; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -295,7 +313,9 @@ &dsi_nt37801_amoled_qsync_video &dsi_nt37801_amoled_fhd_plus_cmd &dsi_nt37801_amoled_cmd_ddicspr - &dsi_nt37801_amoled_video_ddicspr>; + &dsi_nt37801_amoled_video_ddicspr + &dsi_sharp_qhd_plus_dsc_cmd + &dsi_sharp_qhd_plus_dsc_video>; }; }; @@ -314,6 +334,8 @@ &dsi_nt37801_amoled_qsync_video &dsi_nt37801_amoled_fhd_plus_cmd &dsi_nt37801_amoled_cmd_ddicspr - &dsi_nt37801_amoled_video_ddicspr>; + &dsi_nt37801_amoled_video_ddicspr + &dsi_sharp_qhd_plus_dsc_cmd + &dsi_sharp_qhd_plus_dsc_video>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index cb197717..98eaab75 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -20,6 +20,8 @@ #include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-dsc-10bit-cmd.dtsi" @@ -792,6 +794,30 @@ }; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <4 4 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <4 4 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sim_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; From 7d2f2106a6cd58308b19c35eea2227ad0b3d4198 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Mon, 11 Nov 2024 11:58:50 +0530 Subject: [PATCH 08/12] ARM: dts: msm: add display DT node for Kera target This change adds display DT node for Kera target. Change-Id: I19694c8cd0fc9c684fe21edcd21cd7b5035f502e Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 317 ++++++++++++++++++++++++++++++++++ display/kera-sde-display.dtsi | 9 +- display/kera-sde.dtsi | 64 +++++++ 3 files changed, 389 insertions(+), 1 deletion(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index 4f0e2247..b3621384 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -7,6 +7,323 @@ &soc { mdss_mdp: qcom,mdss_mdp@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x400000 0x2000>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "ipcc_reg"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + #cooling-cells = <2>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x488>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>; + qcom,sde-ctl-size = <0x1000>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x0f0f 0x0f0f + 0x0f0f 0x0f0f>; + qcom,sde-mixer-size = <0x400>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none", "none", "none"; + + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", + "dcwb", "dcwb", "dcwb", "dcwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x8c>; + + qcom,sde-dspp-off = <0x55000 0x57000 0x59000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010001>; + qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dspp-rc-min-region-width = <20>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,sde-dest-scaler-top-off = <0x0008F000>; + qcom,sde-dest-scaler-top-size = <0x1C>; + qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + + qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; + qcom,sde-intf-size = <0x4BC>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 + 0x67000 0x67400 0x7f000 0x7f400>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0x2c>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x67700 0x7f700>; + qcom,sde-merge-3d-size = <0x1c>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x240>; + + qcom,sde-dsc-off = <0x81000 0x81000 0x82000>; + qcom,sde-dsc-size = <0x8>; + qcom,sde-dsc-pair-mask = <2 1 0>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00>; + qcom,sde-dsc-ctl-size = <0x24>; + qcom,sde-dsc-native422-supp = <1 1 1>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 + 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x344>; + + qcom,sde-sspp-xin-id = <0 4 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 6 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7>; + + qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130 + 0x160 0x190 0x1c0 0x1f0 0x220>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000 + 4300000 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x4330 0>, <0x6330 0>, + <0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>; + qcom,sde-sspp-clk-status = + <0x4334 0>, <0x6334 0>, + <0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3004>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <5120>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-dsc-linewidth = <2560>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <8192>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x8 0x2>; + qcom,sde-ubwc-version = <0x40000000>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <6800000>; + qcom,sde-max-bw-high-kbps = <14200000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-num-ddr-channels = <2>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00020000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600>; + qcom,sde-dspp-demura-size = <0x150>; + qcom,sde-dspp-demura-version = <0x00030000>; + + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x80>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1074>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>; + + qcom,sde-vbif-default-ot-rd-limit = <40>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>; + + qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>; + + qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001 + 0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>; + + qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x0 0x77776541 0x0 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0x7>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x800>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00030000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 14000>, + <0 140000>, + <0 310000>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0x700>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x700>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00050000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone = <0x900 0x00020000>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00060000>; + qcom,sde-dspp-gc = <0x17c0 0x00020000>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; }; mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index 2159dfde..cbb5d7de 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -7,6 +7,13 @@ #include "kera-sde-display-common.dtsi" &soc { + sde_wb2: qcom,wb-display@2 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display2"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; }; &sde_dsi { @@ -68,7 +75,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 83cf63be..f9a5b91c 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -9,6 +9,8 @@ #include #include #include "kera-sde-common.dtsi" +#include +#include &soc { ext_disp: qcom,msm-ext-disp { @@ -177,9 +179,71 @@ }; }; }; + + smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { + iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_sec 0x0 0x00020000>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x2>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; }; &mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + + clock-names = "gcc_bus", + "iface_clk", "branch_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 660000000 660000000 19200000 660000000>; + clock-max-rate = <0 0 660000000 660000000 19200000 660000000>; + + qcom,hw-fence-sw-version = <0x1>; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + qti,smmu-proxy-cb-id = ; + + qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + + qcom,sde-has-idle-pc; + + qcom,sde-ib-bw-vote = <2500000 0 1600000>; + qcom,sde-dspp-ltm-version = <0x00010003>; + /* offsets are based off dspp 0, 1, 2, and 3 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300>; }; &mdss_dsi0 { From 91808d9891afdd2cb946203ca8bb88af87280d27 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 5 Nov 2024 07:41:22 +0530 Subject: [PATCH 09/12] ARM: dts: msm: enable display on kera trustedvm platforms Enable display on kera trustedvm platforms. Change-Id: I76a769baa8726f24a391b612b6558d8322e96527 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- ...trustedvm-kera-sde-display-atp-overlay.dts | 18 ++ ...trustedvm-kera-sde-display-cdp-overlay.dts | 18 ++ display/trustedvm-kera-sde-display-cdp.dtsi | 156 ++++++++++++++++++ ...trustedvm-kera-sde-display-mtp-overlay.dts | 19 +++ display/trustedvm-kera-sde-display-mtp.dtsi | 156 ++++++++++++++++++ ...trustedvm-kera-sde-display-qrd-overlay.dts | 18 ++ display/trustedvm-kera-sde-display-qrd.dtsi | 156 ++++++++++++++++++ ...trustedvm-kera-sde-display-rcm-overlay.dts | 19 +++ ...rustedvm-kera-sde-display-rumi-overlay.dts | 17 ++ display/trustedvm-kera-sde-display-rumi.dtsi | 10 ++ display/trustedvm-kera-sde-display.dtsi | 28 ++++ display/trustedvm-kera-sde.dtsi | 44 +++++ 12 files changed, 659 insertions(+) create mode 100644 display/trustedvm-kera-sde-display-atp-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-cdp-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-cdp.dtsi create mode 100644 display/trustedvm-kera-sde-display-mtp-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-mtp.dtsi create mode 100644 display/trustedvm-kera-sde-display-qrd-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-qrd.dtsi create mode 100644 display/trustedvm-kera-sde-display-rcm-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-rumi-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-rumi.dtsi create mode 100644 display/trustedvm-kera-sde-display.dtsi create mode 100644 display/trustedvm-kera-sde.dtsi diff --git a/display/trustedvm-kera-sde-display-atp-overlay.dts b/display/trustedvm-kera-sde-display-atp-overlay.dts new file mode 100644 index 00000000..362e7d57 --- /dev/null +++ b/display/trustedvm-kera-sde-display-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM ATP"; + compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap", + "qcom,atp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/trustedvm-kera-sde-display-cdp-overlay.dts b/display/trustedvm-kera-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..07e44da0 --- /dev/null +++ b/display/trustedvm-kera-sde-display-cdp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM CDP"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; +}; diff --git a/display/trustedvm-kera-sde-display-cdp.dtsi b/display/trustedvm-kera-sde-display-cdp.dtsi new file mode 100644 index 00000000..77b43890 --- /dev/null +++ b/display/trustedvm-kera-sde-display-cdp.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/trustedvm-kera-sde-display-mtp-overlay.dts b/display/trustedvm-kera-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..073f3342 --- /dev/null +++ b/display/trustedvm-kera-sde-display-mtp-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM MTP"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, + <0x30008 1>; +}; diff --git a/display/trustedvm-kera-sde-display-mtp.dtsi b/display/trustedvm-kera-sde-display-mtp.dtsi new file mode 100644 index 00000000..77b43890 --- /dev/null +++ b/display/trustedvm-kera-sde-display-mtp.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/trustedvm-kera-sde-display-qrd-overlay.dts b/display/trustedvm-kera-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..e2f6b39c --- /dev/null +++ b/display/trustedvm-kera-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM QRD"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/display/trustedvm-kera-sde-display-qrd.dtsi b/display/trustedvm-kera-sde-display-qrd.dtsi new file mode 100644 index 00000000..77b43890 --- /dev/null +++ b/display/trustedvm-kera-sde-display-qrd.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/trustedvm-kera-sde-display-rcm-overlay.dts b/display/trustedvm-kera-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..20c01be8 --- /dev/null +++ b/display/trustedvm-kera-sde-display-rcm-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RCM"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, + <0x30015 1>; +}; diff --git a/display/trustedvm-kera-sde-display-rumi-overlay.dts b/display/trustedvm-kera-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..0374cc20 --- /dev/null +++ b/display/trustedvm-kera-sde-display-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,msm-id = <659 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/trustedvm-kera-sde-display-rumi.dtsi b/display/trustedvm-kera-sde-display-rumi.dtsi new file mode 100644 index 00000000..6bf94fae --- /dev/null +++ b/display/trustedvm-kera-sde-display-rumi.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; diff --git a/display/trustedvm-kera-sde-display.dtsi b/display/trustedvm-kera-sde-display.dtsi new file mode 100644 index 00000000..e6420a52 --- /dev/null +++ b/display/trustedvm-kera-sde-display.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&sde_dsi1 { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; +}; diff --git a/display/trustedvm-kera-sde.dtsi b/display/trustedvm-kera-sde.dtsi new file mode 100644 index 00000000..9b88fd38 --- /dev/null +++ b/display/trustedvm-kera-sde.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "kera-sde-common.dtsi" + +&soc { +}; + +&mdss_mdp { +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; From 738b90d9fe7b934d8910f9a5ba773b22637cf124 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Fri, 1 Nov 2024 16:05:56 +0530 Subject: [PATCH 10/12] ARM: dts: msm: enable display on kera platforms Enable display on kera platforms. Change-Id: I40b6a9f002a72a527e2cbe61f0f59f059ad5716e Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- Kbuild | 10 + ...-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi | 156 +++ ...anel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi | 134 +++ ...-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi | 262 +++++ ...anel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi | 134 +++ display/kera-sde-display-atp-overlay.dts | 17 + display/kera-sde-display-cdp-overlay.dts | 17 + display/kera-sde-display-cdp.dtsi | 185 ++++ display/kera-sde-display-common.dtsi | 942 ++++++++++++++++++ display/kera-sde-display-mtp-overlay.dts | 18 + display/kera-sde-display-mtp.dtsi | 185 ++++ display/kera-sde-display-pinctrl.dtsi | 114 +++ display/kera-sde-display-qrd-overlay.dts | 17 + display/kera-sde-display-qrd.dtsi | 185 ++++ display/kera-sde-display-rcm-overlay.dts | 18 + display/kera-sde-display-rumi-overlay.dts | 16 + display/kera-sde-display-rumi.dtsi | 11 + display/kera-sde-display.dtsi | 8 +- display/kera-sde.dtsi | 2 - 19 files changed, 2425 insertions(+), 6 deletions(-) create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi create mode 100644 display/kera-sde-display-atp-overlay.dts create mode 100644 display/kera-sde-display-cdp-overlay.dts create mode 100644 display/kera-sde-display-cdp.dtsi create mode 100644 display/kera-sde-display-common.dtsi create mode 100644 display/kera-sde-display-mtp-overlay.dts create mode 100644 display/kera-sde-display-mtp.dtsi create mode 100644 display/kera-sde-display-pinctrl.dtsi create mode 100644 display/kera-sde-display-qrd-overlay.dts create mode 100644 display/kera-sde-display-qrd.dtsi create mode 100644 display/kera-sde-display-rcm-overlay.dts create mode 100644 display/kera-sde-display-rumi-overlay.dts create mode 100644 display/kera-sde-display-rumi.dtsi diff --git a/Kbuild b/Kbuild index 7d9c2e52..3c212c66 100644 --- a/Kbuild +++ b/Kbuild @@ -49,6 +49,16 @@ dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-tuna-sde-display-atp-overlay.dtbo display/trustedvm-tuna-sde-display-rcm-overlay.dtbo endif +ifneq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-$(CONFIG_ARCH_KERA) += display/kera-sde.dtbo \ + display/kera-sde-display-atp-overlay.dtbo \ + display/kera-sde-display-cdp-overlay.dtbo \ + display/kera-sde-display-mtp-overlay.dtbo \ + display/kera-sde-display-qrd-overlay.dtbo \ + display/kera-sde-display-rumi-overlay.dtbo \ + display/kera-sde-display-rcm-overlay.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi new file mode 100644 index 00000000..17c9b05f --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_60hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_60hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <353116800>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi new file mode 100644 index 00000000..806b30eb --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_60hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_60hz_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi new file mode 100644 index 00000000..d465d706 --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_90hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_90hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <529675200>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <529675200>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi new file mode 100644 index 00000000..286080d3 --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_90hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_90hz_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/kera-sde-display-atp-overlay.dts b/display/kera-sde-display-atp-overlay.dts new file mode 100644 index 00000000..055789c5 --- /dev/null +++ b/display/kera-sde-display-atp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera ATP"; + compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap", + "qcom,atp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/kera-sde-display-cdp-overlay.dts b/display/kera-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..52f5b3d9 --- /dev/null +++ b/display/kera-sde-display-cdp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera CDP"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; +}; diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi new file mode 100644 index 00000000..e4091be5 --- /dev/null +++ b/display/kera-sde-display-cdp.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi new file mode 100644 index 00000000..f6710815 --- /dev/null +++ b/display/kera-sde-display-common.dtsi @@ -0,0 +1,942 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" + +#include "kera-sde-display-pinctrl.dtsi" + +&soc { + dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "dummy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3544000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <300>; + qcom,supply-post-on-sleep = <1>; + qcom,supply-post-off-sleep = <2>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1250000>; + qcom,supply-enable-load = <200000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-post-off-sleep = <2>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 17 0>; + qcom,panel-te-source = <0>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0122e700 0x00000471>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 121 0>; + qcom,panel-te-source = <1>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0 0x0>; + }; +}; + +/* PHY TIMINGS REVISION YL with reduced margins */ + +&dsi_vtdr6130_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-dyn-clk-enable; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,poms-align-panel-vsync; + + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd-vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@2 { /* FHD+ 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 02 04 00 1a 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@3 { /* HD 60FPS cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <48>; + }; + + timing@4 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 26 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@5 { /* FHD+ 180 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 28 16 + 17 14 02 04 00 43 1b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <96>; + }; + + timing@6 { /* FHD+ 240 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 6f 1f 1f 38 31 1d + 1f 19 02 04 00 55 23]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <110>; + }; + + timing@7 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3e 0f 0f 22 1f 0f + 10 0e 02 04 00 30 14]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <40>; + }; + + timing@8 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 47 12 13 27 22 12 + 13 10 02 04 00 37 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <60>; + }; + + timing@9 { /* WQHD 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0D 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@10 { /* WQHD 5FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1D 1A 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@11 { /* WQHD 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@12 { /* WQHD 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 10 1d 03 + 03 02 02 04 00 0b 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <15>; + }; + + timing@13 { /* WQHD 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <22>; + }; + + timing@14 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@15 { /* WQHD 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@16 { /* WQHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@17 { /* WQHD 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 20 1d 0e + 0e 0d 02 04 00 2c 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@18 { /* WQHD 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f + 10 0e 02 04 00 2f 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,qsync-enable; + qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>; + qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a + 0a 09 02 04 00 1e 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 02 02 04 00 0b 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@1 { /* FHD+ 60fps cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 + 08 08 02 04 00 19 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD+ 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2a 0b 0b 1c 1a 0b + 0c 0b 02 04 00 23 10]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* FHD+ 240FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0e 21 1d 0f + 0f 0d 02 04 00 2e 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD+ 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@7 { /* FHD+ 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@8 { /* FHD+ 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 + 01 01 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@9 { /* FHD+ 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@10 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 12 1e 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11 + 12 0f 02 04 00 35 16]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 40FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 5K 80FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17 + 18 14 02 04 00 43 1c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD 60FPS 24bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 60FPS 30bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 03 03 02 04 00 0d 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03 + 03 02 02 04 00 0a 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@17 { /* WQHD 144 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e + 04 04 03 02 04 00 0e 09]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/kera-sde-display-mtp-overlay.dts b/display/kera-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..1eb193fa --- /dev/null +++ b/display/kera-sde-display-mtp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera MTP"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, + <0x30008 1>; +}; diff --git a/display/kera-sde-display-mtp.dtsi b/display/kera-sde-display-mtp.dtsi new file mode 100644 index 00000000..e4091be5 --- /dev/null +++ b/display/kera-sde-display-mtp.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/kera-sde-display-pinctrl.dtsi b/display/kera-sde-display-pinctrl.dtsi new file mode 100644 index 00000000..0a7180d8 --- /dev/null +++ b/display/kera-sde-display-pinctrl.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_dsi1_active: sde_dsi1_active { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi1_suspend: sde_dsi1_suspend { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio17"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio17"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio121"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio121"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; diff --git a/display/kera-sde-display-qrd-overlay.dts b/display/kera-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..04a7ea38 --- /dev/null +++ b/display/kera-sde-display-qrd-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera QRD"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/display/kera-sde-display-qrd.dtsi b/display/kera-sde-display-qrd.dtsi new file mode 100644 index 00000000..e4091be5 --- /dev/null +++ b/display/kera-sde-display-qrd.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/kera-sde-display-rcm-overlay.dts b/display/kera-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..24277d00 --- /dev/null +++ b/display/kera-sde-display-rcm-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RCM"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, + <0x30015 1>; +}; diff --git a/display/kera-sde-display-rumi-overlay.dts b/display/kera-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..8c8643b2 --- /dev/null +++ b/display/kera-sde-display-rumi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,msm-id = <659 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/kera-sde-display-rumi.dtsi b/display/kera-sde-display-rumi.dtsi new file mode 100644 index 00000000..177e852b --- /dev/null +++ b/display/kera-sde-display-rumi.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; + diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index cbb5d7de..f2942b9c 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -19,8 +19,8 @@ &sde_dsi { clocks = <&mdss_dsi_phy0 0>, <&mdss_dsi_phy0 1>, - <&mdss_dsi_phy1 2>, - <&mdss_dsi_phy1 3>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, /* * Currently the dsi clock handles are under the dsi * controller DT node. As soon as the controller probe @@ -48,8 +48,8 @@ &sde_dsi1 { clocks = <&mdss_dsi_phy0 0>, <&mdss_dsi_phy0 1>, - <&mdss_dsi_phy1 2>, - <&mdss_dsi_phy1 3>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, /* * Currently the dsi clock handles are under the dsi * controller DT node. As soon as the controller probe diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index f9a5b91c..b18d8140 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -248,7 +248,6 @@ &mdss_dsi0 { vdda-1p2-supply = <&L4B>; - qcom,split-link-supported; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -262,7 +261,6 @@ &mdss_dsi1 { vdda-1p2-supply = <&L4B>; - qcom,split-link-supported; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, From 51764b0a87edb2e413503fe81633fb38d649b1dd Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Sun, 17 Nov 2024 15:00:36 +0530 Subject: [PATCH 11/12] ARM: dts: msm: add smmu_sde_unsec to connector list This change adds smmu_sde_unsec to connector list for trustedvm platform in tuna target. Change-Id: I86cba1f15319a502450f8b89b9bb96409869a821 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/trustedvm-tuna-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/trustedvm-tuna-sde-display.dtsi b/display/trustedvm-tuna-sde-display.dtsi index 22b2e5b0..56e90443 100644 --- a/display/trustedvm-tuna-sde-display.dtsi +++ b/display/trustedvm-tuna-sde-display.dtsi @@ -24,5 +24,5 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>; }; From 4d9b336136db4c40ebf3688dcc41e9ba39aa4f44 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Fri, 15 Nov 2024 10:53:05 +0530 Subject: [PATCH 12/12] ARM: dts: msm: enable touch support for Kera display Enable touch support for Kera on CDP, MTP and QRD platforms. Change-Id: Ica6505a62ca407001b6cbaaac8d5b738acd92fc7 Signed-off-by: Anand Tarakh Signed-off-by: lnxdisplay --- display/kera-sde-display-cdp.dtsi | 15 +++++++++++++++ display/kera-sde-display-mtp.dtsi | 15 +++++++++++++++ display/kera-sde-display-qrd.dtsi | 15 +++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index e4091be5..efb7d0d3 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -183,3 +183,18 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/display/kera-sde-display-mtp.dtsi b/display/kera-sde-display-mtp.dtsi index e4091be5..efb7d0d3 100644 --- a/display/kera-sde-display-mtp.dtsi +++ b/display/kera-sde-display-mtp.dtsi @@ -183,3 +183,18 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/display/kera-sde-display-qrd.dtsi b/display/kera-sde-display-qrd.dtsi index e4091be5..efb7d0d3 100644 --- a/display/kera-sde-display-qrd.dtsi +++ b/display/kera-sde-display-qrd.dtsi @@ -183,3 +183,18 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +};