From 7ba4fef4ece5726411833d3eb26f1fc612cf1fdb Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Tue, 7 Jan 2025 16:21:51 +0530 Subject: [PATCH] ARM: dts: msm: Update Reference Clock to clk8_a4 for Kera UFS 2.x The Kera UFS 2.x requires a reference clock of 19.2MHz. Currently, the reference clock provided by the DTSI node RPMH_LN_BB_CLK3 returns clk_get_rate() as 38.4MHz. To address this, the handler is updated to use clk8_a4, ensuring the clock rate is set to 19.2MHz. Change-Id: I92ad772c7b86652c0dc5bdc3af18a9db900d74e5 Signed-off-by: Manish Pandey Signed-off-by: Vishvanath Singh --- qcom/kera_ufs2.dtsi | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/qcom/kera_ufs2.dtsi b/qcom/kera_ufs2.dtsi index 320ed23f..da26508c 100644 --- a/qcom/kera_ufs2.dtsi +++ b/qcom/kera_ufs2.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -57,5 +57,36 @@ qcom,vccq2-parent-supply = <&S1B>; qcom,vccq2-parent-max-microamp = <210000>; + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&clk8_a4>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "ok"; };