Merge "ARM: dts: msm: Add SDIO support for monaco"

qcom/monaco-idp-v1-common.dtsi

@@ -24,6 +24,34 @@
 	qcom,vdd-io-current-level = <0 250000>;
 };
 
+&sdhc_3 {
+	/* device core power supply for sd card*/
+	vdd-supply = <&L26A>;
+	qcom,vdd-voltage-level = <3304000 3304000>;
+	qcom,vdd-current-level = <200 570000>;
+
+	/* device communication power supply for msm_io*/
+	vdd-io-supply = <&L16A>;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-current-level = <200 22000>;
+
+	keep-power-in-suspend;
+	non-removable;
+	qcom,core_3_0v_support;
+	qcom,restore-after-cx-collapse;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc3_clk_on &sdc3_cmd_on &sdc3_data_on>;
+	pinctrl-1 = <&sdc3_clk_off &sdc3_cmd_off &sdc3_data_off>;
+
+	/* forbid SDR104/SDR50/DDR50 for hi3881 */
+	sdhci-caps-mask = <0x7 0x0>;
+	qcom,devfreq,freq-table = <400000 20000000 25000000 50000000>;
+	max-frequency = <50000000>;
+
+	status = "disabled";
+};
+
 &pm5100_sdam_2 {
 	hap_cl_brake: cl_brake@7c {
 		reg = <0x7c 0x1>;

qcom/monaco-pinctrl.dtsi

@@ -1478,6 +1478,90 @@
 			};
 		};
 
+		pmx_sdc3_clk {
+			sdc3_clk_on: sdc3_clk_on {
+				mux {
+					pins = "gpio79";
+					function = "sdc3_clk";
+					};
+
+				config {
+					pins = "gpio79";
+					drive-strength = <8>; /* 8 MA */
+					bias-disable; /* NO pull */
+					};
+			};
+
+			sdc3_clk_off: sdc3_clk_off {
+				mux {
+					pins = "gpio79";
+					function = "sdc3_clk";
+					};
+
+				config {
+					pins = "gpio79";
+					bias-disable; /* NO pull */
+					drive-strength = <2>; /* 2 MA */
+				};
+			};
+		};
+
+		pmx_sdc3_cmd {
+			sdc3_cmd_on: sdc3_cmd_on {
+				mux {
+					pins = "gpio78";
+					function = "sdc3_cmd";
+				};
+
+				config {
+					pins = "gpio78";
+					bias-pull-up; /* pull up */
+					drive-strength = <8>; /* 8 MA */
+				};
+			};
+
+			sdc3_cmd_off: sdc3_cmd_off {
+				mux {
+					pins = "gpio78";
+					function = "sdc3_cmd";
+				};
+
+				config {
+					pins = "gpio78";
+					bias-pull-up; /* pull up */
+					drive-strength = <2>; /* 2 MA */
+				};
+			};
+		};
+
+		pmx_sdc3_data {
+			sdc3_data_on: sdc3_data_on {
+				mux {
+					pins = "gpio74","gpio75","gpio76","gpio77";
+					function = "sdc3_data";
+				};
+
+				config {
+					pins = "gpio74","gpio75","gpio76","gpio77";
+					bias-pull-up; /* pull up */
+					drive-strength = <8>; /* 8 MA */
+				};
+			};
+
+			sdc3_data_off: sdc3_data_off {
+				mux {
+					pins = "gpio74","gpio75","gpio76","gpio77";
+					function = "sdc3_data";
+				};
+
+				config {
+					pins = "gpio74","gpio75","gpio76","gpio77";
+					bias-pull-up; /* pull up */
+					drive-strength = <2>; /* 2 MA */
+				};
+			};
+		};
+
 		pmx_ts_int_active {
 			ts_int_active: ts_int_active {
 				mux {

qcom/monaco.dtsi

@@ -26,6 +26,7 @@
 
 	aliases {
 		mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
+		sdhc2 = &sdhc_3; /*SDC3 SDIO slot*/
 		serial0 = &qupv3_se6_2uart;
 		hsuart0 = &qupv3_se5_4uart;
 		i2c1 = &qupv3_se1_i2c;
@@ -1824,6 +1825,55 @@
 		};
 	};
 
+	sdhc_3: sdhci@4784000 {
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x04784000 0x1000>;
+		reg-names = "hc_mem";
+
+		interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
+		clock-names = "core", "iface";
+
+		interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>;
+		interconnect-names = "sdhc-ddr","cpu-sdhc";
+		qcom,msm-bus,name = "sdhc3";
+		qcom,msm-bus,num-cases = <8>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-KBps =
+			/* No Vote */
+			<0 0>, <0 0>,
+			/* 400 KB/s*/
+			<1046 3200>, <1600 1600>,
+			/* 25 MB/s */
+			<65360 250000>, <100000 133320>,
+			/* 50 MB/s */
+			<130718 250000>, <133320 133320>,
+			/* 100 MB/s */
+			<261438 250000>, <150000 133320>,
+			/* 200 MB/s */
+			<261438 800000>, <300000 300000>,
+			/* Max. bandwidth */
+			<1338562 4096000>, <1338562 4096000>;
+			qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
+				100000000 200000000 4294967295>;
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>;
+
+		bus-width = <4>;
+
+		iommus = <&apps_smmu 0xA0 0x0>;
+		qcom,iommu-dma = "bypass";
+
+		qcom,devfreq,freq-table = <400000 20000000 25000000 50000000>;
+
+		status = "disabled";
+	};
+
 	mpm: interrupt-controller@45f01b8 {
 		compatible = "qcom,mpm-monaco", "qcom,mpm";
 		interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;