diff --git a/Kbuild b/Kbuild index ad1766ed..07fcf44a 100644 --- a/Kbuild +++ b/Kbuild @@ -2,6 +2,7 @@ ifeq ($(CONFIG_ARCH_SUN),y) dtbo-y += nxp/sun-nfc.dtbo \ nxp/sun-nfc-cdp.dtbo \ nxp/sun-nfc-mtp.dtbo \ + nxp/tuna-nfc.dtbo \ dtbo-y += st/sun-nfc.dtbo \ st/sun-nfc-mtp.dtbo \ @@ -11,7 +12,8 @@ dtbo-y += st/sun-nfc.dtbo \ st/sun-nfc-qrd-sku2-v8.dtbo \ st/sun-nfc-atp.dtbo \ st/sun-mtp-kiwi-v8.dtbo \ - st/sun-nfc-rcm.dtbo + st/sun-nfc-rcm.dtbo \ + st/tuna-nfc.dtbo endif ifeq ($(CONFIG_ARCH_PARROT),y) @@ -30,6 +32,7 @@ dtbo-y += nxp/ravelin-nfc.dtbo \ nxp/ravelin-nfc-atp.dtbo endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/nxp/tuna-nfc-common.dtsi b/nxp/tuna-nfc-common.dtsi new file mode 100644 index 00000000..4874d49b --- /dev/null +++ b/nxp/tuna-nfc-common.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include "tuna-nfc-pinctrl.dtsi" + +&qupv3_se0_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 55 0x00>; + qcom,sn-ven = <&tlmm 114 0x00>; + qcom,sn-clkreq = <&tlmm 115 0x00>; + qcom,sn-szone = "enable"; + interrupt-parent = <&tlmm>; + interrupts = <55 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; diff --git a/nxp/tuna-nfc-pinctrl.dtsi b/nxp/tuna-nfc-pinctrl.dtsi new file mode 100644 index 00000000..fa234eff --- /dev/null +++ b/nxp/tuna-nfc-pinctrl.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* Enable, and Clock request gpios */ + pins = "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + pins = "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; //nfc +}; //tlmm diff --git a/nxp/tuna-nfc.dts b/nxp/tuna-nfc.dts new file mode 100644 index 00000000..9dab700a --- /dev/null +++ b/nxp/tuna-nfc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Tuna SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <33 0>, <1 0>, <8 0>, <11 0>, <21 0>; +}; diff --git a/st/tuna-nfc-common.dtsi b/st/tuna-nfc-common.dtsi new file mode 100644 index 00000000..58dcdf18 --- /dev/null +++ b/st/tuna-nfc-common.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-nfc-pinctrl.dtsi" + +&qupv3_se0_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + st21nfc: st21nfc@08 { + compatible = "st,st21nfc"; + reg = <0x08>; + irq-gpios = <&tlmm 55 0x00>; + reset-gpios = <&tlmm 114 0x00>; + clkreq-gpios = <&tlmm 115 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <55 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; diff --git a/st/tuna-nfc-pinctrl.dtsi b/st/tuna-nfc-pinctrl.dtsi new file mode 100644 index 00000000..fa234eff --- /dev/null +++ b/st/tuna-nfc-pinctrl.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* Enable, and Clock request gpios */ + pins = "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + pins = "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; //nfc +}; //tlmm diff --git a/st/tuna-nfc.dts b/st/tuna-nfc.dts new file mode 100644 index 00000000..9dab700a --- /dev/null +++ b/st/tuna-nfc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Tuna SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <33 0>, <1 0>, <8 0>, <11 0>, <21 0>; +};