From 48829df0fe4f9ccfa44a5b4c84aa9d5e7ab37b36 Mon Sep 17 00:00:00 2001 From: Sanskar Omar Date: Fri, 17 Jan 2025 11:15:41 +0530 Subject: [PATCH 1/3] ARM: dts: msm: Add fps entry for kera Add fps entry for kera. Change-Id: I04ff258f3d36345f9c618a3745253371a9e49420 Signed-off-by: Sanskar Omar --- qcom/kera.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 0336cdbc..c759ae2b 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1671,6 +1671,10 @@ reg = <0x0118 0x4>; }; + feat_conf18: feat_conf18@0148 { + reg = <0x0148 0x4>; + }; + gpu_speed_bin: gpu_speed_bin@138 { reg = <0x138 0x2>; bits = <0 9>; @@ -1684,8 +1688,8 @@ qfprom_sys: qfprom@0 { compatible = "qcom,qfprom-sys"; - nvmem-cells = <&feat_conf6>; - nvmem-cell-names = "feat_conf6"; + nvmem-cells = <&feat_conf6>, <&feat_conf18>; + nvmem-cell-names = "feat_conf6", "feat_conf18"; }; wpss_pas: remoteproc-wpss@97000000 { From 379051569e35d62df1ee4f93e8275f7f66ed2a12 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Fri, 17 Jan 2025 07:58:03 +0530 Subject: [PATCH 2/3] ARM: dts: msm: Add pcie and display voter devices for KERA Add pcie and display CRM voters for kera. This will allow interconnect providers to target their votes on CESTA DRV for meeting cesta client bandwidth constraints. Change-Id: I16198f67ca4a8f7b2d3704044704b78bd267e2f3 Signed-off-by: Raviteja Laggyshetty --- qcom/kera.dtsi | 127 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 117 insertions(+), 10 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index c759ae2b..4b59ed17 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -2017,18 +2017,93 @@ qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, <&cpufreq_hw 2>; }; + pcie_crm_hw_0_bcm_voter: bcm_voter@0 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "pcie_crm"; + qcom,crm-client-idx = <0>; + qcom,crm-pwr-states = <5>; + }; + + disp_crm_hw_0_bcm_voter: bcm_voter@1 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <0>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_1_bcm_voter: bcm_voter@2 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <1>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_2_bcm_voter: bcm_voter@3 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <2>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_3_bcm_voter: bcm_voter@4 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <3>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_4_bcm_voter: bcm_voter@5 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <4>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_5_bcm_voter: bcm_voter@6 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <5>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_sw_0_bcm_voter: bcm_voter@7 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-sw-client; + qcom,crm-client-idx = <0>; + qcom,crm-pwr-states = <1>; + }; + clk_virt: interconnect@0 { compatible = "qcom,kera-clk_virt"; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "pcie_crm_hw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>; }; mc_virt: interconnect@1 { compatible = "qcom,kera-mc_virt"; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "pcie_crm_hw_0", + "disp_crm_hw_0", + "disp_crm_hw_1", + "disp_crm_hw_2", + "disp_crm_hw_3", + "disp_crm_hw_4", + "disp_crm_hw_5", + "disp_crm_sw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>, + <&disp_crm_hw_0_bcm_voter>, + <&disp_crm_hw_1_bcm_voter>, + <&disp_crm_hw_2_bcm_voter>, + <&disp_crm_hw_3_bcm_voter>, + <&disp_crm_hw_4_bcm_voter>, + <&disp_crm_hw_5_bcm_voter>, + <&disp_crm_sw_0_bcm_voter>; }; config_noc: interconnect@1600000 { @@ -2059,8 +2134,10 @@ compatible = "qcom,kera-pcie_anoc"; reg = <0x16c0000 0x11400>; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "pcie_crm_hw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>; clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; }; @@ -2087,16 +2164,46 @@ compatible = "qcom,kera-mmss_noc"; reg = <0x1780000 0x7d800>; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "disp_crm_hw_0", + "disp_crm_hw_1", + "disp_crm_hw_2", + "disp_crm_hw_3", + "disp_crm_hw_4", + "disp_crm_hw_5", + "disp_crm_sw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&disp_crm_hw_0_bcm_voter>, + <&disp_crm_hw_1_bcm_voter>, + <&disp_crm_hw_2_bcm_voter>, + <&disp_crm_hw_3_bcm_voter>, + <&disp_crm_hw_4_bcm_voter>, + <&disp_crm_hw_5_bcm_voter>, + <&disp_crm_sw_0_bcm_voter>; }; gem_noc: interconnect@24100000 { compatible = "qcom,kera-gem_noc"; reg = <0x24100000 0x163080>; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "pcie_crm_hw_0", + "disp_crm_hw_0", + "disp_crm_hw_1", + "disp_crm_hw_2", + "disp_crm_hw_3", + "disp_crm_hw_4", + "disp_crm_hw_5", + "disp_crm_sw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>, + <&disp_crm_hw_0_bcm_voter>, + <&disp_crm_hw_1_bcm_voter>, + <&disp_crm_hw_2_bcm_voter>, + <&disp_crm_hw_3_bcm_voter>, + <&disp_crm_hw_4_bcm_voter>, + <&disp_crm_hw_5_bcm_voter>, + <&disp_crm_sw_0_bcm_voter>; }; nsp_noc: interconnect@320c0000 { From e3fe7b6fe798860d096d874a98056e0bb9c7fb39 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Thu, 23 Jan 2025 16:01:51 +0530 Subject: [PATCH 3/3] ARM: dts: msm: Update regulator support for tuna Add RET mode support for L2G/L3G for tuna platforms as per the sleep setting recommendation. While at it set init mode as LPM for L3G and L6K regulators. As clients always vote for 0 load, the regulator framework will not apply it and the HPM init-mode will not change, leading to higher power consumption. So update the LPM for L3G and L6K regulators. Change-Id: I5b210ac3e9ffee94889c2390becfaa5eb6c235ab Signed-off-by: Kavya Nunna --- qcom/tuna-regulators.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/qcom/tuna-regulators.dtsi b/qcom/tuna-regulators.dtsi index 157ecf02..fd609de8 100644 --- a/qcom/tuna-regulators.dtsi +++ b/qcom/tuna-regulators.dtsi @@ -953,9 +953,10 @@ qcom,resource-name = "ldog2"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 30000>; + qcom,mode-threshold-currents = <0 10000 30000>; L2G: pm_v6g_l2: vreg-pm_v6g-l2 { regulator-name = "pm_v6g_l2"; @@ -973,9 +974,10 @@ qcom,resource-name = "ldog3"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 30000>; + qcom,mode-threshold-currents = <0 10000 30000>; L3G: pm_v6g_l3: vreg-pm_v6g-l3 { regulator-name = "pm_v6g_l3"; @@ -983,7 +985,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; qcom,init-voltage = <1800000>; - qcom,init-mode = ; + qcom,init-mode = ; }; }; @@ -1123,7 +1125,7 @@ regulator-min-microvolt = <1100000>; regulator-max-microvolt = <2000000>; qcom,init-voltage = <1776000>; - qcom,init-mode = ; + qcom,init-mode = ; }; };