From 09fde6cbb77670fbc40a16bda4d39072067ce315 Mon Sep 17 00:00:00 2001 From: Mohammed Ahmed Date: Wed, 11 Sep 2024 15:04:12 -0700 Subject: [PATCH] ARM: dts: msm: Add canoe target dts files Add canoe target dts files Change-Id: Iffee5ea6e1679c564e29a560c715b9a3c5df3300 CRs-Fixed: 3922164 --- canoe-kiwi-cnss.dts | 19 ++++ canoe-kiwi-cnss.dtsi | 225 ++++++++++++++++++++++++++++++++++++++++++ canoe-peach-cnss.dts | 20 ++++ canoe-peach-cnss.dtsi | 215 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 479 insertions(+) create mode 100644 canoe-kiwi-cnss.dts create mode 100644 canoe-kiwi-cnss.dtsi create mode 100644 canoe-peach-cnss.dts create mode 100644 canoe-peach-cnss.dtsi diff --git a/canoe-kiwi-cnss.dts b/canoe-kiwi-cnss.dts new file mode 100644 index 00000000..7fbc39ed --- /dev/null +++ b/canoe-kiwi-cnss.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "canoe-kiwi-cnss.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Canoe SoCs"; + compatible = "qcom,canoe", "qcom,canoep", "qcom,canoe-mtp", "qcom,canoe-cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x20001 0>, <0x20008 0>, <0x40015 0>; +}; diff --git a/canoe-kiwi-cnss.dtsi b/canoe-kiwi-cnss.dtsi new file mode 100644 index 00000000..75f8daf5 --- /dev/null +++ b/canoe-kiwi-cnss.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl { + mux { + pins = "gpio18"; + function = "wcn_sw_ctrl"; + }; + }; + + cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx { + mux { + pins = "gpio19"; + function = "wcn_sw"; + }; + }; + }; +}; + +&reserved_memory { + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + }; +}; + +&soc { + wlan_kiwi: qcom,cnss-kiwi@b0000000 { + compatible = "qcom,cnss-kiwi"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>; + + supported-ids = <0x1107>; + wlan-en-gpio = <&tlmm 16 0>; + qcom,bt-en-gpio = <&pm8550vs_f_gpios 3 0>; + qcom,sw-ctrl-gpio = <&tlmm 18 0>; + /* List of GPIOs to be setup for interrupt wakeup capable */ + mpm_wake_set_gpios = <18 19>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl", + "sw_ctrl_wl_cx"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + pinctrl-2 = <&cnss_wlan_sw_ctrl>; + pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>; + qcom,wlan; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x780000>; + cnss-enable-self-recovery; + qcom,wlan-cbc-enabled; + use-pm-domain; + qcom,same-dt-multi-dev; + /* For AOP communication, use direct QMP instead of mailbox */ + qcom,qmp = <&aoss_qmp>; + + vdd-wlan-io-supply = <&L3F>; + qcom,vdd-wlan-io-config = <1800000 1800000 30000 0 1>; + vdd-wlan-io12-supply = <&L2F>; + qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>; + vdd-wlan-supply = <&S4J>; + qcom,vdd-wlan-config = <932000 1000000 0 0 0>; + vdd-wlan-aon-supply = <&S4D>; + qcom,vdd-wlan-aon-config = <976000 1036000 0 0 1>; + vdd-wlan-dig-supply = <&S1D>; + qcom,vdd-wlan-dig-config = <916000 1100000 0 0 1>; + vdd-wlan-rfa1-supply = <&S3G>; + qcom,vdd-wlan-rfa1-config = <1864000 2000000 0 0 1>; + vdd-wlan-rfa2-supply = <&S7I>; + qcom,vdd-wlan-rfa2-config = <1316000 1340000 0 0 1>; + vdd-wlan-ant-share-supply = <&L6K>; + qcom,vdd-wlan-ant-share-config = <1800000 1800000 0 0 1>; + + interconnects = + <&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>, + <&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; + + qcom,icc-path-count = <2>; + qcom,bus-bw-cfg-count = <9>; + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz */ + <2250 800000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz */ + <7500 800000>, + /* medium: 60-240 Mbps snoc/anoc: 100 Mhz */ + <30000 800000>, + /* high: 240-1200 Mbps snoc/anoc: 100 Mhz */ + <100000 800000>, + /* very high: > 1200 Mbps snoc/anoc: 403 Mhz */ + <175000 3224000>, + /* ultra high: DBS mode snoc/anoc: 403 Mhz */ + <312500 3224000>, + /* super high: DBS mode snoc/anoc: 533 Mhz */ + <587500 4264000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */ + <7500 1600000>, + + /** ICC Path 2 **/ + <0 0>, + /* idle: 0-18 Mbps ddr: 547.2 MHz */ + <2250 2188800>, + /* low: 18-60 Mbps ddr: 547.2 MHz */ + <7500 2188800>, + /* medium: 60-240 Mbps ddr: 547.2 MHz */ + <30000 2188800>, + /* high: 240-1200 Mbps ddr: 547.2 MHz */ + <100000 2188800>, + /* very high: > 1200 Mbps ddr: 1555 MHz */ + <175000 6220800>, + /* ultra high: DBS mode ddr: 2092 MHz */ + <312500 8368000>, + /* super high: DBS mode ddr: 3.2 GHz */ + <587500 12800000>, + /* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */ + <7500 2188800>; + + qcom,vreg_pdc_map = + "s4j", "bb", + "s4d", "bb", + "s3g", "rf", + "s7i", "rf", + "s1d", "rf"; + + qcom,pmu_vreg_map = + "VDD095_MX_PMU", "s4d", + "VDD095_PMU", "s4j", + "VDD_PMU_AON_I", "s1d", + "VDD095_PMU_BT", "s1d", + "VDD09_PMU_RFA_I", "s1d", + "VDD13_PMU_PCIE_I", "s7i", + "VDD13_PMU_RFA_I", "s7i", + "VDD19_PMU_PCIE_I", "s3g", + "VDD19_PMU_RFA_I", "s3g"; + + qcom,pdc_init_table = + "{class: wlan_pdc, ss: rf, res: s3g.v, upval: 1856}", + "{class: wlan_pdc, ss: rf, res: s3g.v, dwnval: 1844}", + "{class: wlan_pdc, ss: rf, res: s7i.v, upval: 1316}", + "{class: wlan_pdc, ss: rf, res: s7i.v, dwnval: 972}", + "{class: wlan_pdc, ss: rf, res: s1d.m, enable: 1}", + "{class: wlan_pdc, ss: rf, res: s1d.v, enable: 1}", + "{class: wlan_pdc, ss: rf, res: s1d.v, upval: 916}", + "{class: wlan_pdc, ss: rf, res: s1d.v, dwnval: 880}", + "{class: wlan_pdc, ss: rf, res: s4j.m, enable: 0}", + "{class: wlan_pdc, ss: rf, res: s4j.v, enable: 0}", + "{class: wlan_pdc, ss: bb, res: s4d.v, upval: 976}", + "{class: wlan_pdc, ss: bb, res: s4d.v, dwnval: 536}", + "{class: wlan_pdc, ss: bb, res: s4j.m, enable: 1}", + "{class: wlan_pdc, ss: bb, res: s4j.v, enable: 1}", + "{class: wlan_pdc, ss: bb, res: s4j.v, upval: 932}", + "{class: wlan_pdc, ss: bb, res: s4j.v, dwnval: 444}"; + + /* cpu mask used for wlan tx rx interrupt affinity + * + */ + wlan-txrx-intr-cpumask = <0x3 0x30>; + }; +}; + +&pcie0_rp { + + cnss_pci0: cnss_pci0 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group0>; + memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition { + /* address-cells =3 size-cells=2 from sun-pcie.dtsi */ + iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x98000000>, + <&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>; + }; + + cnss_pci_iommu_group0: cnss_pci_iommu_group0 { + qcom,iommu-msi-size = <0x1000>; + qcom,iommu-geometry = <0x98000000 0x18010000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + qcom,iommu-faults = "stall-disable", "HUPCF", + "non-fatal"; + }; + }; +}; diff --git a/canoe-peach-cnss.dts b/canoe-peach-cnss.dts new file mode 100644 index 00000000..90dfecb8 --- /dev/null +++ b/canoe-peach-cnss.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "canoe-peach-cnss.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoCs"; + compatible = "qcom,canoe", "qcom,canoep"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, + <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <1 0>, <8 0>, <0x1000B 0>, <0x15 0>; +}; diff --git a/canoe-peach-cnss.dtsi b/canoe-peach-cnss.dtsi new file mode 100644 index 00000000..6d4ff475 --- /dev/null +++ b/canoe-peach-cnss.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl { + mux { + pins = "gpio18"; + function = "wcn_sw_ctrl"; + }; + }; + + cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx { + mux { + pins = "gpio19"; + function = "wcn_sw"; + }; + }; + + cnss_host_sol_default: cnss_host_sol_default { + mux { + pins = "gpio202"; + function = "gpio"; + }; + + config { + pins = "gpio202"; + drive-strength = <4>; + bias-pull-down; + }; + }; + }; +}; + +&reserved_memory { + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + }; +}; + +&soc { + wlan_peach: qcom,cnss-peach@b0000000 { + compatible = "qcom,cnss-peach"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>; + + supported-ids = <0x110E>; + wlan-en-gpio = <&tlmm 16 0>; + qcom,bt-en-gpio = <&pm8550vs_f_gpios 3 0>; + qcom,sw-ctrl-gpio = <&tlmm 18 0>; + wlan-host-sol-gpio = <&tlmm 202 0>; + wlan-dev-sol-gpio = <&tlmm 203 0>; + /* List of GPIOs to be setup for interrupt wakeup capable */ + mpm_wake_set_gpios = <18 19>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl", + "sw_ctrl_wl_cx", "sol_default"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + pinctrl-2 = <&cnss_wlan_sw_ctrl>; + pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>; + pinctrl-4 = <&cnss_host_sol_default>; + qcom,wlan; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x780000>; + cnss-enable-self-recovery; + qcom,wlan-cbc-enabled; + use-pm-domain; + qcom,same-dt-multi-dev; + /* For AOP communication, use direct QMP instead of mailbox */ + qcom,qmp = <&aoss_qmp>; + msix-match-addr = <0x3000>; + + vdd-wlan-io-supply = <&L3F>; + qcom,vdd-wlan-io-config = <1800000 1800000 30000 0 1>; + vdd-wlan-io12-supply = <&L2F>; + qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>; + vdd-wlan-aon-supply = <&S4D>; + qcom,vdd-wlan-aon-config = <876000 1036000 0 0 1>; + vdd-wlan-dig-supply = <&S4J>; + qcom,vdd-wlan-dig-config = <876000 1000000 0 0 1>; + vdd-wlan-rfa1-supply = <&S3G>; + qcom,vdd-wlan-rfa1-config = <1860000 2000000 0 0 1>; + vdd-wlan-rfa2-supply = <&S7I>; + qcom,vdd-wlan-rfa2-config = <1312000 1340000 0 0 1>; + vdd-wlan-ant-share-supply = <&L6K>; + qcom,vdd-wlan-ant-share-config = <1800000 1860000 0 0 1>; + + interconnects = + <&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>, + <&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; + + qcom,icc-path-count = <2>; + qcom,bus-bw-cfg-count = <9>; + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz */ + <2250 800000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz */ + <7500 800000>, + /* medium: 60-240 Mbps snoc/anoc: 100 Mhz */ + <30000 800000>, + /* high: 240-1200 Mbps snoc/anoc: 100 Mhz */ + <100000 800000>, + /* very high: > 1200 Mbps snoc/anoc: 403 Mhz */ + <175000 3224000>, + /* ultra high: DBS mode snoc/anoc: 403 Mhz */ + <312500 3224000>, + /* super high: DBS mode snoc/anoc: 533 Mhz */ + <587500 4264000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */ + <7500 1600000>, + + /** ICC Path 2 **/ + <0 0>, + /* idle: 0-18 Mbps ddr: 547.2 MHz */ + <2250 2188800>, + /* low: 18-60 Mbps ddr: 547.2 MHz */ + <7500 2188800>, + /* medium: 60-240 Mbps ddr: 547.2 MHz */ + <30000 2188800>, + /* high: 240-1200 Mbps ddr: 547.2 MHz */ + <100000 2188800>, + /* very high: > 1200 Mbps ddr: 1555 MHz */ + <175000 6220800>, + /* ultra high: DBS mode ddr: 2092 MHz */ + <312500 8368000>, + /* super high: DBS mode ddr: 3.2 GHz */ + <587500 12800000>, + /* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */ + <7500 2188800>; + + qcom,vreg_pdc_map = + "s4j", "rf", + "s4d", "bb", + "s3g", "rf", + "s7i", "rf"; + + qcom,pmu_vreg_map = + "VDDD_AON_0P9", "s4j", + "VDDA_RFA_1P9", "s3g", + "VDDA_RFA_1P3", "s7i", + "VDDA_RFA_0P9", "s4j", + "VDDD_WLMX_0P9", "s4d", + "VDDD_WLCX_0P9", "s4j", + "VDDD_BTCX_0P9", "s4j", + "VDDD_BTCMX_0P9", "s4j", + "VDDA_PCIE_1P2", "s7i", + "VDDA_PCIE_0P9", "s7i"; + + qcom,pdc_init_table = + "{class: wlan_pdc, ss: rf, res: s4j.m, enable: 1}", + "{class: wlan_pdc, ss: rf, res: s4j.v, enable: 1}", + "{class: wlan_pdc, ss: rf, res: s4j.v, upval: 876}", + "{class: wlan_pdc, ss: rf, res: s4j.v, dwnval: 876}"; + + /* cpu mask used for wlan tx rx interrupt affinity + * + */ + wlan-txrx-intr-cpumask = <0x3 0x30>; + }; +}; + +&pcie0_rp { + cnss_pci0: cnss_pci0 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_audio_iommu_group0>; + memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>; + + cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition { + /* address-cells =3 size-cells=2 from sun-pcie.dtsi */ + iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x18000000>, + <&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>; + }; + }; +};