diff --git a/bindings/clock/qcom,camcc-parrot.yaml b/bindings/clock/qcom,camcc-parrot.yaml new file mode 100644 index 00000000..0c64ac18 --- /dev/null +++ b/bindings/clock/qcom,camcc-parrot.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,camcc-parrot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller + +maintainers: + - Kalpak Kawadkar + +description: | + Camera clock control module which supports the clocks, resets and + power domains on Parrot. + + See also: + - dt-bindings/clock/qcom,camcc-parrot.h + +properties: + compatible: + const: qcom,parrot-camcc + + clocks: + items: + - description: Board XO source + - description: Camera AHB clock from GCC + + clock-names: + items: + - const: bi_tcxo + - const: iface + + vdd_cx-supply: + description: Phandle pointer to the vdd_cx logic rail supply + + vdd_mxa-supply: + description: Phandle pointer to the vdd_mxa logic rail supply + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: "qcom,gcc.yaml#" + +unevaluatedProperties: false + +examples: + - | + #include + camcc: clock-controller@ade0000 { + compatible = "qcom,parrot-camcc", "syscon"; + reg = <0xade0000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index 8a8426dc..4f3b0dd8 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,pineapple-debugcc - qcom,sun-debugcc + - qcom,parrot-debugcc clocks: items: diff --git a/bindings/clock/qcom,dispcc-parrot.yaml b/bindings/clock/qcom,dispcc-parrot.yaml new file mode 100644 index 00000000..33282157 --- /dev/null +++ b/bindings/clock/qcom,dispcc-parrot.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-parrot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Display Clock & Reset Controller + +maintainers: + - Jagadeesh Kona + +description: | + Qualcomm Technologies, Inc. display clock control module which supports the clocks and + power domains on Parrot. + + See also: + dt-bindings/clock/qcom,dispcc-parrot.h + +properties: + compatible: + enum: + - qcom,parrot-dispcc + + clocks: + items: + - description: Brard XO source + - description: Brard XO_AO source + - description: Sleep clock source + - description: AHB config clock from GCC + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: iface + + vdd_cx-supply: + description: Phandle pointer to the vdd_cx logic rail supply + + vdd_mxa-supply: + description: Phandle pointer to the vdd_mxa logic rail supply + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + dispcc: clock-controller@af00000 { + compatible = "qcom,parrot-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,gcc-parrot.yaml b/bindings/clock/qcom,gcc-parrot.yaml new file mode 100644 index 00000000..983dbbef --- /dev/null +++ b/bindings/clock/qcom,gcc-parrot.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-parrot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Global Clock & Reset Controller + +maintainers: + - Taniya Das + +description: | + Global clock control module which supports the clocks, resets and + power domains on Parrot. + + See also: + - dt-bindings/clock/qcom,gcc-parrot.h + +properties: + compatible: + const: qcom,parrot-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source (Optional clock) + - description: UFS Phy Rx symbol 0 clock source (Optional clock) + - description: UFS Phy Rx symbol 1 clock source (Optional clock) + - description: UFS Phy Tx symbol 0 clock source (Optional clock) + - description: USB3 Phy wrapper pipe clock source (Optional clock) + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + - const: pcie_0_pipe_clk # Optional clock + - const: ufs_phy_rx_symbol_0_clk # Optional clock + - const: ufs_phy_rx_symbol_1_clk # Optional clock + - const: ufs_phy_tx_symbol_0_clk # Optional clock + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock + minItems: 2 + + vdd_cx-supply: + description: Phandle pointer to the vdd_cx logic rail supply + + vdd_mxa-supply: + description: Phandle pointer to the vdd_mxa logic rail supply + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: "qcom,gcc.yaml#" + +unevaluatedProperties: false + +examples: + - | + #include + gcc: clock-controller@100000 { + compatible = "qcom,parrot-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", "sleep_clk", + "pcie_0_pipe_clk", "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,gpucc.yaml b/bindings/clock/qcom,gpucc.yaml index e27be44a..bfcedac6 100644 --- a/bindings/clock/qcom,gpucc.yaml +++ b/bindings/clock/qcom,gpucc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding +title: Qualcomm Technologies, Inc. Graphics Clock & Reset Controller maintainers: - Taniya Das @@ -23,6 +23,7 @@ description: | dt-bindings/clock/qcom,gpucc-sm8250.h dt-bindings/clock/qcom,gpucc-pineapple.h dt-bindings/clock/qcom,gpucc-sun.h + dt-bindings/clock/qcom,gpucc-parrot.h properties: compatible: @@ -37,6 +38,7 @@ properties: - qcom,sm8250-gpucc - qcom,pineapple-gpucc - qcom,sun-gpucc + - qcom,parrot-gpucc clocks: items: diff --git a/bindings/clock/qcom,rpmhcc.yaml b/bindings/clock/qcom,rpmhcc.yaml index ad7912e7..d87b775d 100644 --- a/bindings/clock/qcom,rpmhcc.yaml +++ b/bindings/clock/qcom,rpmhcc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,rpmhcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. RPMh Clocks Bindings +title: Qualcomm Technologies, Inc. RPMh Clocks maintainers: - Taniya Das @@ -32,6 +32,7 @@ properties: - qcom,sm8450-rpmh-clk - qcom,pineapple-rpmh-clk - qcom,sun-rpmh-clk + - qcom,parrot-rpmh-clk clocks: maxItems: 1 diff --git a/bindings/clock/qcom,videocc.yaml b/bindings/clock/qcom,videocc.yaml index 0b54473a..d9f1ad18 100644 --- a/bindings/clock/qcom,videocc.yaml +++ b/bindings/clock/qcom,videocc.yaml @@ -21,6 +21,7 @@ description: | dt-bindings/clock/qcom,videocc-sm8250.h dt-bindings/clock/qcom,videocc-pineapple.h dt-bindings/clock/qcom,videocc-sun.h + dt-bindings/clock/qcom,videocc-parrot.h properties: compatible: @@ -34,6 +35,7 @@ properties: - qcom,pineapple-videocc-v2 - qcom,sun-videocc - qcom,sun-videocc-v2 + - qcom,parrot-videocc clocks: items: