diff --git a/bindings/dsi.txt b/bindings/dsi.txt deleted file mode 100644 index a3f2fc10..00000000 --- a/bindings/dsi.txt +++ /dev/null @@ -1,278 +0,0 @@ -Qualcomm Technologies Inc. snapdragon DSI output - -DSI Controller: -Required properties: -- compatible: - * "qcom,mdss-dsi-ctrl" -- reg: Physical base address and length of the registers of controller -- reg-names: The names of register regions. The following regions are required: - * "dsi_ctrl" -- interrupts: The interrupt signal from the DSI block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: Phandles to device clocks. -- clock-names: the following clocks are required: - * "mdp_core" - * "iface" - * "bus" - * "core_mmss" - * "byte" - * "pixel" - * "core" - For DSIv2, we need an additional clock: - * "src" - For DSI6G v2.0 onwards, we need also need the clock: - * "byte_intf" -- assigned-clocks: Parents of "byte" and "pixel" for the given platform. -- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided - by a DSI PHY block. See [1] for details on clock bindings. -- vdd-supply: phandle to vdd regulator device node -- vddio-supply: phandle to vdd-io regulator device node -- vdda-supply: phandle to vdda regulator device node -- phys: phandle to DSI PHY device node -- phy-names: the name of the corresponding PHY device -- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) -- ports: Contains 2 DSI controller ports as child nodes. Each port contains - an endpoint subnode as defined in [2] and [3]. - -Optional properties: -- panel@0: Node of panel connected to this DSI controller. - See files in [4] for each supported panel. -- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is - driving a panel which needs 2 DSI links. -- qcom,master-dsi: Boolean value indicating if the DSI controller is driving - the master link of the 2-DSI panel. -- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is - driving a 2-DSI panel whose 2 links need receive command simultaneously. -- pinctrl-names: the pin control state names; should contain "default" -- pinctrl-0: the default pinctrl state (active) -- pinctrl-n: the "sleep" pinctrl state -- ports: contains DSI controller input and output ports as children, each - containing one endpoint subnode. -- qcom,dsi-ctrl-shared: Boolean value indicating if the DSI controller is - shared between dual displays. - - DSI Endpoint properties: - - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's - input endpoint. For port@1, set to the MDP interface output. See [2] for - device graph info. - - - data-lanes: this describes how the physical DSI data lanes are mapped - to the logical lanes on the given platform. The value contained in - index n describes what physical lane is mapped to the logical lane n - (DATAn, where n lies between 0 and 3). The clock lane position is fixed - and can't be changed. Hence, they aren't a part of the DT bindings. See - [3] for more info on the data-lanes property. - - For example: - - data-lanes = <3 0 1 2>; - - The above mapping describes that the logical data lane DATA0 is mapped to - the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2 - to phys DATA1 and logic DATA3 to phys DATA2. - - There are only a limited number of physical to logical mappings possible: - <0 1 2 3> - <1 2 3 0> - <2 3 0 1> - <3 0 1 2> - <0 3 2 1> - <1 0 3 2> - <2 1 0 3> - <3 2 1 0> - -DSI PHY: -Required properties: -- compatible: Could be the following - * "qcom,dsi-phy-28nm-hpm" - * "qcom,dsi-phy-28nm-lp" - * "qcom,dsi-phy-20nm" - * "qcom,dsi-phy-28nm-8960" - * "qcom,dsi-phy-14nm" - * "qcom,dsi-phy-10nm" -- reg: Physical base address and length of the registers of PLL, PHY. Some - revisions require the PHY regulator base address, whereas others require the - PHY lane base address. See below for each PHY revision. -- reg-names: The names of register regions. The following regions are required: - For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_regulator" - For DSI 14nm and 10nm PHYs: - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_lane" -- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating - 2 clocks: A byte clock (index 0), and a pixel clock (index 1). -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: Phandles to device clocks. See [1] for details on clock bindings. -- clock-names: the following clocks are required: - * "iface" - For 28nm HPM/LP, 28nm 8960 PHYs: -- vddio-supply: phandle to vdd-io regulator device node - For 20nm PHY: -- vddio-supply: phandle to vdd-io regulator device node -- vcca-supply: phandle to vcca regulator device node - For 14nm PHY: -- vcca-supply: phandle to vcca regulator device node - For 10nm PHY: -- vdds-supply: phandle to vdds regulator device node - -Optional properties: -- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY - regulator is wanted. -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split is enabled, this time should not be higher - than two times the dsi link rate time. - If the property is not specified, then the default value is 14000 us. - -- frame-threshold-time-us: For command mode panels, this specifies the idle - time for dsi controller where no active data is - send to the panel, as controller is done sending - active pixels. If there is no desired DSI clocks - specified, then clocks will be derived from this - threshold time, which has a default value in chipset - based on the CPU processing power. - -- dsi_pll_codes: Contain an u32 array data to store dsi pll codes which were passed - from UEFI. -- qcom,dsi-phy-shared: Boolean value indicating if the DSI phy is shared - between dual displays. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/graph.txt -[3] Documentation/devicetree/bindings/media/video-interfaces.txt -[4] Documentation/devicetree/bindings/display/panel/ - -Example: - dsi0: dsi@fd922800 { - compatible = "qcom,mdss-dsi-ctrl"; - qcom,dsi-host-index = <0>; - interrupt-parent = <&mdp>; - interrupts = <4 0>; - reg-names = "dsi_ctrl"; - reg = <0xfd922800 0x200>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "bus", - "byte", - "core", - "core_mmss", - "iface", - "mdp_core", - "pixel"; - clocks = - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_ESC0_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_PCLK0_CLK>; - - assigned-clocks = - <&mmcc BYTE0_CLK_SRC>, - <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = - <&dsi_phy0 0>, - <&dsi_phy0 1>; - - vdda-supply = <&pma8084_l2>; - vdd-supply = <&pma8084_l22>; - vddio-supply = <&pma8084_l12>; - - phys = <&dsi_phy0>; - phy-names ="dsi-phy"; - - qcom,dual-dsi-mode; - qcom,master-dsi; - qcom,sync-dual-dsi; - qcom,dsi-ctrl-shared; - - qcom,mdss-mdp-transfer-time-us = <12000>; - frame-threshold-time-us = <800>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dsi_active>; - pinctrl-1 = <&dsi_suspend>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel: panel@0 { - compatible = "sharp,lq101r1sx01"; - reg = <0>; - link2 = <&secondary>; - - power-supply = <...>; - backlight = <...>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - }; - - dsi_phy0: dsi-phy@fd922a00 { - compatible = "qcom,dsi-phy-28nm-hpm"; - qcom,dsi-phy-index = <0>; - reg-names = - "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - reg = <0xfd922a00 0xd4>, - <0xfd922b00 0x2b0>, - <0xfd922d80 0x7b>; - clock-names = "iface"; - clocks = <&mmcc MDSS_AHB_CLK>; - #clock-cells = <1>; - vddio-supply = <&pma8084_l12>; - - qcom,dsi-phy-regulator-ldo-mode; - qcom,panel-allow-phy-poweroff; - qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>; - qcom,panel-force-clock-lane-hs; - pll_codes_region = <&dsi_pll_codes_data>; - qcom,dsi-phy-shared; - }; - - dsi_pll_codes_data:dsi_pll_codes { - reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; - label = "dsi_pll_codes"; - }; diff --git a/bindings/dsi.yaml b/bindings/dsi.yaml new file mode 100644 index 00000000..4fc3c0a6 --- /dev/null +++ b/bindings/dsi.yaml @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc. Snapdragon DSI Controller output + +description: > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + [2] Documentation/devicetree/bindings/graph.txt + [3] Documentation/devicetree/bindings/media/video-interfaces.txt + [4] Documentation/devicetree/bindings/display/panel/ + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +properties: + compatible: + const: qcom,mdss-dsi-ctrl + + reg: + description: Physical base address and length of the registers of controller + + reg-names: + description: The names of register regions. + required: + - "dsi_ctrl" + + interrupts: + description: The interrupt signal from the DSI block. + + power-domains: + const: <&mmcc MDSS_GDSC> + + clocks: + description: Phandles to device clocks. + $ref: /schemas/types.yaml#/definitions/phandle + + clock-names: + description: > + Clocks necessary for DSI operation. For DSIv2, we need an additional clock "src" and for + DSI6G v2.0 onwards, we also need the clock "byte_intf". + required: + - "mdp_core" + - "iface" + - "bus" + - "core_mmss" + - "byte" + - "pixel" + - "core" + + assigned-clocks: + description: Parents of "byte" and "pixel" for the given platform. + + assigned-clock-parents: + description: > + The Byte clock and Pixel clock PLL outputs provided + by a DSI PHY block. See [1] for details on clock bindings. + + vdd-supply: + description: phandle to vdd regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + vddio-supply: + description: phandle to vdd-io regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + vdda-supply: + description: phandle to vdda regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + phys: + description: phandle to DSI PHY device node + $ref: /schemas/types.yaml#/definitions/phandle + + phy-names: + description: the name of the corresponding PHY device + $ref: /schemas/types.yaml#/definitions/string-array + + syscon-sfpb: + description: A phandle to mmss_sfpb syscon node (only for DSIv2) + $ref: /schemas/types.yaml#/definitions/phandle + + panel@0: + description: > + Node of panel connected to this DSI controller. + See files in [4] for each supported panel. + + qcom,dual-dsi-mode: + description: > + Boolean value indicating if the DSI controller is + driving a panel which needs 2 DSI links. + + qcom,master-dsi: + description: > + Boolean value indicating if the DSI controller is driving + the master link of the 2-DSI panel. + + qcom,sync-dual-dsi: + description: > + Boolean value indicating if the DSI controller is + driving a 2-DSI panel whose 2 links need receive command simultaneously. + + pinctrl-names: + description: the pin control state names; should contain "default" + + pinctrl-0: + description: the default pinctrl state (active) + + pinctrl-n: + description: the "sleep" pinctrl state + + qcom,dsi-ctrl-shared: + description: > + Boolean value indicating if the DSI controller is + shared between dual displays. + +required: + - compatible + - reg + - reg-names + - interrupts + - power-domains + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - vdd-supply + - vddio-supply + - vdda-supply + - phys + - phy-names + - syscon-sfpb + - ports + +examples: + - | + dsi0: dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + qcom,dsi-host-index = <0>; + interrupt-parent = <&mdp>; + interrupts = <4 0>; + reg-names = "dsi_ctrl"; + reg = <0xfd922800 0x200>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = + "bus", + "byte", + "core", + "core_mmss", + "iface", + "mdp_core", + "pixel"; + clocks = + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_PCLK0_CLK>; + + assigned-clocks = + <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = + <&dsi_phy0 0>, + <&dsi_phy0 1>; + + vdda-supply = <&pma8084_l2>; + vdd-supply = <&pma8084_l22>; + vddio-supply = <&pma8084_l12>; + + phys = <&dsi_phy0>; + phy-names ="dsi-phy"; + + qcom,dual-dsi-mode; + qcom,master-dsi; + qcom,sync-dual-dsi; + qcom,dsi-ctrl-shared; + + qcom,mdss-mdp-transfer-time-us = <12000>; + frame-threshold-time-us = <800>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dsi_active>; + pinctrl-1 = <&dsi_suspend>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + panel: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + link2 = <&secondary>; + + power-supply = <...>; + backlight = <...>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/bindings/dsi_phy.yaml b/bindings/dsi_phy.yaml new file mode 100644 index 00000000..7d99e278 --- /dev/null +++ b/bindings/dsi_phy.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dsi_phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc. Snapdragon DSI PHY output + +description: > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + [2] Documentation/devicetree/bindings/graph.txt + [3] Documentation/devicetree/bindings/media/video-interfaces.txt + [4] Documentation/devicetree/bindings/display/panel/ + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +properties: + compatible: + enum: + - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-lp + - qcom,dsi-phy-20nm + - qcom,dsi-phy-28nm-8960 + - qcom,dsi-phy-14nm + - qcom,dsi-phy-10nm + + reg: + description: > + Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. + + reg-names: + description: > + The names of register regions. For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY "dsi_phy_regulator" + is needed and for DSI 14nm and 10nm PHYs "dsi_phy_lane" is needed. + required: + - "dsi_pll" + - "dsi_phy" + + clock-cells: + description: > + Must be 1. The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + const: <&mmcc MDSS_GDSC> + + clocks: + description: Phandles to device clocks. See [1] for details on clock bindings. + $ref: /schemas/types.yaml#/definitions/phandle + + clock-names: + const: iface + $ref: /schemas/types.yaml#/definitions/string-array + + vddio-supply: + description: > + For 28nm HPM/LP, 28nm 8960 PHYs and 20nm PHY, this is phandle to vdd-io regulator + device node + $ref: /schemas/types.yaml#/definitions/phandle + + vcca-supply: + description: For 14nm PHY and 20nm PHY this is phandle to vcca regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + vdds-supply: + description: For 10nm PHY , phandle to vdds regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,dsi-phy-regulator-ldo-mode: + description: Boolean value indicating if the LDO mode PHY regulator is wanted. + + qcom,mdss-mdp-transfer-time-us: + description: > + Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. + $ref: /schemas/types.yaml#/definitions/uint32 + + frame-threshold-time-us: + description: > + For command mode panels, this specifies the idle + time for dsi controller where no active data is + send to the panel, as controller is done sending + active pixels. If there is no desired DSI clocks + specified, then clocks will be derived from this + threshold time, which has a default value in chipset + based on the CPU processing power. + $ref: /schemas/types.yaml#/definitions/uint32 + + dsi_pll_codes: + description: Contain an u32 array data to store dsi pll codes which were passed from UEFI. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,dsi-phy-shared: + description: Boolean value indicating if the DSI phy is shared between dual displays. + +required: + - compatible + - reg + - reg-names + - clock-cells + - power-domains + - clocks + - clock-names + - vddio-supply + - vcca-supply + - vdds-supply + +examples: + - | + dsi_phy0: dsi-phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-hpm"; + qcom,dsi-phy-index = <0>; + reg-names = + "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x2b0>, + <0xfd922d80 0x7b>; + clock-names = "iface"; + clocks = <&mmcc MDSS_AHB_CLK>; + #clock-cells = <1>; + vddio-supply = <&pma8084_l12>; + + qcom,dsi-phy-regulator-ldo-mode; + qcom,panel-allow-phy-poweroff; + qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>; + qcom,panel-force-clock-lane-hs; + pll_codes_region = <&dsi_pll_codes_data>; + qcom,dsi-phy-shared; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +... diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt deleted file mode 100644 index c65c61e1..00000000 --- a/bindings/mdss-dsi-panel.txt +++ /dev/null @@ -1,1005 +0,0 @@ -QTI mdss-dsi-panel - -mdss-dsi-panel is a dsi panel device which supports panels that -are compatible with MIPI display serial interface specification. - -Required properties: -- compatible: This property applies to DSI V2 panels only. - This property should not be added for panels - that work based on version "V6.0" - DSI panels that are of different versions - are initialized by the drivers for dsi controller. - This property specifies the version - for DSI HW that this panel will work with - "qcom,dsi-panel-v2" = DSI V2.0 -- status: This property applies to DSI V2 panels only. - This property should not be added for panels - that work based on version "V6.0" - DSI panels that are of different versions - are initialized by the drivers for dsi controller. - A string that has to be set to "okay/ok" - to enable the panel driver. By default this property - will be set to "disable". Will be set to "ok/okay" - status for specific platforms. -- qcom,mdss-dsi-panel-controller: Specifies the phandle for the DSI controller that - this panel will be mapped to. -- qcom,mdss-dsi-panel-width: Specifies panel width in pixels. -- qcom,mdss-dsi-panel-height: Specifies panel height in pixels. -- qcom,mdss-dsi-bpp: Specifies the panel bits per pixel. - 3 = for rgb111 - 8 = for rgb332 - 12 = for rgb444 - 16 = for rgb565 - 18 = for rgb666 - 24 = for rgb888 -- qcom,mdss-dsi-panel-destination: A string that specifies the destination display for the panel. - "display_1" = DISPLAY_1 - "display_2" = DISPLAY_2 -- qcom,mdss-dsi-panel-timings: An array of length 12 that specifies the PHY - timing settings for the panel. -- qcom,mdss-dsi-panel-timings-8996: An array of length 40 char that specifies the 8996 PHY lane - timing settings for the panel. -- qcom,mdss-dsi-on-command: A byte stream formed by multiple dcs packets base on - qcom dsi controller protocol. - byte 0: dcs data type - byte 1: Unused - byte 2: virtual channel number - byte 3: Message flags - byte 4: wait number of specified ms after dcs command - transmitted - byte 5, 6: 16 bits length in network byte order - byte 7 and beyond: number byte of payload -- qcom,mdss-dsi-off-command: A byte stream formed by multiple dcs packets base on - qcom dsi controller protocol. - byte 0: dcs data type - byte 1: Unused - byte 2: virtual channel number - byte 3: Message flags - byte 4: wait number of specified ms after dcs command - transmitted - byte 5, 6: 16 bits length in network byte order - byte 7 and beyond: number byte of payload -- qcom,mdss-dsi-post-panel-on-command: same as "qcom,mdss-dsi-on-command" except commands are - sent after displaying an image. -- qcom,platform-reset-gpio: Specifies the reset gpio of primary display, not required for simulation panels. - -Note, if a short DCS packet(i.e packet with Byte 0:dcs data type as 05) mentioned in -qcom,mdss-dsi-on-command/qcom,mdss-dsi-off-command stream fails to transmit, -then 3 options can be tried. - 1. Send the packet as a long packet instead - Byte 0: dcs data type = 05 (DCS short Packet) - Byte 0: dcs data type = 29 (DCS long Packet) - 2. Send the packet in one burst by prepending with the next packet in packet stream - Byte 3 = 00 (indicates this is an individual packet) - Byte 3 = 40 (indicates this will be appended to the next - individual packet in the packet stream) - 3. Prepend a NULL packet to the short packet and send both in one burst instead of - combining multiple short packets and sending them in one burst. - -Optional properties: -- cell-index: Timing node index to help driver maintain the device tree ordering. -- qcom,platform-sec-reset-gpio: Specifies the reset gpio of secondary display. -- qcom,platform-bklight-en-gpio: Specifies the gpio for enabling backlight. -- qcom,mdss-dsi-panel-name: A string used as a descriptive name of the panel -- qcom,vid-on-commands: same as "qcom,mdss-dsi-on-command" except commands are - only sent for video mode. -- qcom,vid-on-commands-state: String that specifies the ctrl state for sending panel on commands. - for video mode. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,cmd-on-commands: same as "qcom,mdss-dsi-on-command" except commands are - only sent for command mode. -- qcom,cmd-on-commands-state: String that specifies the ctrl state for sending panel on commands. - for command mode. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-physical-type: A string used as a decriptive type of the panel. - "oled" : That indicate it's an OLED panel. - "lcd" : That indicate it's an LCD panel. - If it is not set, consider it is a LCD panel as default. -- qcom,mdss-dsi-panel-phy-timings: An array of length 'n' char that specifies the DSI PHY lane - timing settings for the panel. This is specific to SDE DRM driver. - The value of 'n' depends on the DSI PHY h/w revision and parsing this - property properly will be taken care in the DSI PHY DRM driver. -- qcom,cmd-sync-wait-broadcast: Boolean used to broadcast dcs command to panels. -- qcom,mdss-dsi-fbc-enable: Boolean used to enable frame buffer compression mode. -- qcom,mdss-dsi-panel-mode-switch: Boolean used to enable panel operating mode switch. -- qcom,poms-align-panel-vsync: Boolean used to align panel TE with timing engine vsync in POMS -- qcom,mdss-dsi-bpp-switch: Boolean used to enable bpp mode switch for non-DSC modes. -- qcom,mdss-dsi-bpp-mode: Specifies the panel bits per pixel per timing node, only used when "qcom,mdss-dsi-bpp-switch" is set. - 24 = for rgb888, default mode if "qcom,mdss-dsi-bpp-mode" is not set. - 30 = for rgb101010. -- qcom,mdss-dsi-fbc-slice-height: Slice height(in lines) of compressed block. - Expressed as power of 2. To set as 128 lines, - this should be set to 7. -- qcom,mdss-dsi-fbc-2d-pred-mode: Boolean to enable 2D map prediction. -- qcom,mdss-dsi-fbc-ver2-mode: Boolean to enable FBC 2.0 that supports 1/3 - compression. -- qcom,mdss-dsi-fbc-bpp: Compressed bpp supported by the panel. - Specified color order is used as default value. -- qcom,mdss-dsi-fbc-packing: Component packing. - 0 = default value. -- qcom,mdss-dsi-fbc-quant-error: Boolean used to enable quantization error calculation. -- qcom,mdss-dsi-fbc-bias: Bias for CD. - 0 = default value. -- qcom,mdss-dsi-fbc-pat-mode: Boolean used to enable PAT mode. -- qcom,mdss-dsi-fbc-vlc-mode: Boolean used to enable VLC mode. -- qcom,mdss-dsi-fbc-bflc-mode: Boolean used to enable BFLC mode. -- qcom,mdss-dsi-fbc-h-line-budget: Per line extra budget. - 0 = default value. -- qcom,mdss-dsi-fbc-budget-ctrl: Extra budget level. - 0 = default value. -- qcom,mdss-dsi-fbc-block-budget: Per block budget. - 0 = default value. -- qcom,mdss-dsi-fbc-lossless-threshold: Lossless mode threshold. - 0 = default value. -- qcom,mdss-dsi-fbc-lossy-threshold: Lossy mode threshold. - 0 = default value. -- qcom,mdss-dsi-fbc-rgb-threshold: Lossy RGB threshold. - 0 = default value. -- qcom,mdss-dsi-fbc-lossy-mode-idx: Lossy mode index value. - 0 = default value. -- qcom,mdss-dsi-fbc-max-pred-err: Max quantization prediction error. - 0 = default value -- qcom,mdss-dsi-h-back-porch: Horizontal back porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-h-front-porch: Horizontal front porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-h-pulse-width: Horizontal pulse width. - 2 = default value. -- qcom,mdss-dsi-h-sync-skew: Horizontal sync skew value. - 0 = default value. -- qcom,mdss-dsi-v-back-porch: Vertical back porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-v-front-porch: Vertical front porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-v-pulse-width: Vertical pulse width. - 2 = default value. -- qcom,mdss-dsi-h-left-border: Horizontal left border in pixel. - 0 = default value -- qcom,mdss-dsi-h-right-border: Horizontal right border in pixel. - 0 = default value -- qcom,mdss-dsi-v-top-border: Vertical top border in pixel. - 0 = default value -- qcom,mdss-dsi-v-bottom-border: Vertical bottom border in pixel. - 0 = default value -- qcom,mdss-dsi-underflow-color: Specifies the controller settings for the - panel under flow color. - 0xff = default value. -- qcom,mdss-dsi-border-color: Defines the border color value if border is present. - 0 = default value. -- qcom,mdss-dsi-panel-jitter: Panel jitter value is expressed in terms of numerator - and denominator. It contains two u32 values - numerator - followed by denominator. The jitter configurition causes - the early wakeup if panel needs to adjust before vsync. - Default jitter value is 2.0%. Max allowed value is 10%. -- qcom,dsi-wd-jitter-enable: Boolean used to enable watchdog jitter in simulator panels -- qcom,dsi-wd-ltj-max-jitter: A u32 pair with numerator and denominator specifying the - maximum jitter over a long time. -- qcom,dsi-wd-ltj-time-sec: A u32 value to specify the time over which the jitter increases. -- qcom,mdss-dsi-panel-prefill-lines: An integer value defines the panel prefill lines required to - calculate the backoff time of rsc. - Default value is 16 lines. Max allowed value is vtotal. -- qcom,mdss-dsi-pan-enable-dynamic-fps: Boolean used to enable change in frame rate dynamically. -- qcom,mdss-dsi-pan-fps-update: A string that specifies when to change the frame rate. - "dfps_suspend_resume_mode"= FPS change request is - implemented during suspend/resume. - "dfps_immediate_clk_mode" = FPS change request is - implemented immediately using DSI clocks. - "dfps_immediate_porch_mode_hfp" = FPS change request is - implemented immediately by changing panel horizontal - front porch values. - "dfps_immediate_porch_mode_vfp" = FPS change request is - implemented immediately by changing panel vertical - front porch values. -- qcom,dsi-supported-dfps-list: List containing all the supported refresh rates. -- qcom,dsi-supported-qsync-min-fps-list: The fps value in this list indicates the qsync min fps - corresponding to the mode in the qcom,dsi-supported-dfps-list with same index. - qcom,dsi-supported-qsync-min-fps-list cannot be defined along with - qcom,mdss-dsi-qsync-min-refresh-rate. "qcom,qsync-enable" property should be - set along with this property. -- qcom,qsync-mode-min-refresh-rate: This u32 property is used to define qsync min fps per timing node instead - of using same qsync min fps for different timing modes. For defining qsync min - fps per timing node, this property should be defined in all timing nodes or else - to define single qsync fps for all modes, - "qcom,mdss-dsi-qsync-min-refresh-rate" property can be used. - "qcom,qsync-enable" property should be set along with this property. -- qcom,dsi-qsync-avr-step-list: The u32 fps values in this optional list indicate the avr step - requirement for qsync/AVR video mode panels. When a late frame is triggered, - AVR will delay the trigger to ensure the frame transfer snaps to the next step - interval. The step rate must be a common multiple of refresh and min-fps rates. - The values in this list should correspond to the dfps-list with same indeces - when DFPS is used, or a single value which applies to all rates. -- qcom,dsi-qsync-mode-avr-step-fps: This u32 property is used to define avr step fps per timing node instead - of using same qsync avr step fps for different timing modes. - For defining avr step fps per timing node, this property should be defined - in all timing nodes or else to define single qsync avr step fps for all modes - use "qcom,mdss-dsi-qsync-avr-step-fps". -- qcom,dsi-qsync-avr-step-fps: A u32 entry to specify avr step rate supported by the panel. - "qcom,qsync-enable" property should be set along with this property. -- qcom,mdss-dsi-transfer-time-us-min Minimum supported mdp transfer time in us. This entry enables support to - dynamically set the transfer time for the given mode within the defined - range. Both min & max must be defined to enable. - qcom,mdss-dsi-transfer-time-us must be greater than this value. -- qcom,mdss-dsi-transfer-time-us-max Maximum supported mdp transfer time in us. This entry enables support to - dynamically set the transfer time for the given mode within the defined - range. Both min & max must be defined to enable. This time should not be - greater than vsync duration. - qcom,mdss-dsi-transfer-time-us must be less than this value. -- qcom,min-refresh-rate: Minimum refresh rate supported by the panel. -- qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh - rate is not specified, then the frame rate of the panel in - qcom,mdss-dsi-panel-framerate is used. -- qcom,dsi-dyn-clk-enable: Boolean to indicate dsi dynamic clock switch feature - is supported. -- qcom,dsi-dyn-clk-type: A string that specifies the sub-type for the dynamic - clk feature. If dyn clk type is not specified, default - value "legacy" is used. - "legacy" = FPS is not maintained after dynamic clock switch. - "constant-fps-adjust-hfp" = FPS is maintained even after - dynamic clock switch by changing panel horizontal front - porch values. - "constant-fps-adjust-vfp" = FPS is maintained even after - dynamic clock switch by changing panel vertical front - porch values. - This dyn-clk-type entry is an optional binding which is - contingent on the enabling of dynamic clock switch. -- qcom,mdss-dsi-bl-pmic-control-type: A string that specifies the implementation of backlight - control for this panel. - "bl_ctrl_pwm" = Backlight controlled by PWM gpio. - "bl_ctrl_wled" = Backlight controlled by WLED. - "bl_ctrl_dcs" = Backlight controlled by DCS commands. - "bl_ctrl_external" = Backlight controlled by externally - other: Unknown backlight control. (default) -- qcom,mdss-dsi-sec-bl-pmic-control-type: A string that specifies the implementation of backlight - control for secondary panel. - "bl_ctrl_pwm" = Backlight controlled by PWM gpio. - "bl_ctrl_wled" = Backlight controlled by WLED. - "bl_ctrl_dcs" = Backlight controlled by DCS commands. - "bl_ctrl_external" = Backlight controlled by externally - other: Unknown backlight control. (default) -- qcom,mdss-dsi-bl-pwm-pmi: Boolean to indicate that PWM control is through second pmic chip. -- qcom,mdss-dsi-bl-pmic-bank-select: LPG channel for backlight. - Required if backlight pmic control type is PWM -- qcom,mdss-dsi-bl-pmic-pwm-frequency: PWM period in microseconds. - Required if backlight pmic control type is PWM -- qcom,mdss-dsi-pwm-gpio: PMIC gpio binding to backlight. - Required if backlight pmic control type is PWM -- qcom,mdss-dsi-bl-min-level: Specifies the min backlight level supported by the panel. - 0 = default value. -- qcom,mdss-dsi-bl-max-level: Specifies the max backlight level supported by the panel. - 255 = default value. -- qcom,mdss-dsi-bl-inverted-dbv: A boolean to specify whether to invert the display brightness value. - When this boolean is set, will inverted display brightness value. -- qcom,bl-dsc-cmd-state: String that specifies the ctrl state for sending dcs brightness commands. - "dsi_hs_mode" = DSI high speed mode (default) - "dsi_lp_mode" = DSI low power mode - If the string was not set, dsi_hs_mode will be set as default mode. -- qcom,mdss-brightness-max-level: Specifies the max brightness level supported. - 255 = default value. -- qcom,bl-update-flag: A string that specifies controls for backlight update of the panel. - "delay_until_first_frame" = Delay backlight update of the panel - until the first frame is received from the HW. -- qcom,mdss-dsi-interleave-mode: Specifies interleave mode. - 0 = default value. -- qcom,mdss-dsi-panel-type: Specifies the panel operating mode. - "dsi_video_mode" = enable video mode (default). - "dsi_cmd_mode" = enable command mode. -- qcom,5v-boost-gpio: Specifies the panel gpio for display 5v boost. -- qcom,mdss-dsi-te-check-enable: Boolean to enable Tear Check configuration. -- qcom,mdss-dsi-te-using-wd: Boolean entry enables the watchdog timer support to generate the vsync signal - for command mode panel. By default, panel TE will be used to generate the vsync. -- qcom,mdss-dsi-te-using-te-pin: Boolean to specify whether using hardware vsync. -- qcom,qsync-enable: Boolean property to indicate if qsync is enabled/disabled. -- qcom,mdss-dsi-qsync-min-refresh-rate: A u32 entry to specify minimum refresh rate supported by the panel to enable qsync feature. - "qcom,qsync-enable" property should be set along with this property. -- qcom,mdss-dsi-qsync-on-commands: String that specifies the commands to enable qsync feature. -- qcom,mdss-dsi-qsync-on-commands-state: String that specifies the ctrl state for sending qsync on commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-qsync-off-commands: String that specifies the commands to disable qsync feature. -- qcom,mdss-dsi-qsync-off-commands-state: String that specifies the ctrl state for sending qsync off commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-te-pin-select: Specifies TE operating mode. - 0 = TE through embedded dcs command - 1 = TE through TE gpio pin. (default) -- qcom,mdss-dsi-te-dcs-command: Inserts the dcs command. - 1 = default value. -- qcom,mdss-dsi-wr-mem-start: DCS command for write_memory_start. - 0x2c = default value. -- qcom,mdss-dsi-wr-mem-continue: DCS command for write_memory_continue. - 0x3c = default value. -- qcom,mdss-dsi-h-sync-pulse: Specifies the pulse mode option for the panel. - 0 = Don't send hsa/he following vs/ve packet(default) - 1 = Send hsa/he following vs/ve packet -- qcom,mdss-dsi-hfp-power-mode: Boolean to determine DSI lane state during - horizontal front porch (HFP) blanking period. -- qcom,mdss-dsi-hbp-power-mode: Boolean to determine DSI lane state during - horizontal back porch (HBP) blanking period. -- qcom,mdss-dsi-hsa-power-mode: Boolean to determine DSI lane state during - horizontal sync active (HSA) mode. -- qcom,mdss-dsi-last-line-interleave Boolean to determine if last line - interleave flag needs to be enabled. -- qcom,mdss-dsi-bllp-eof-power-mode: Boolean to determine DSI lane state during - blanking low power period (BLLP) EOF mode. -- qcom,mdss-dsi-bllp-power-mode: Boolean to determine DSI lane state during - blanking low power period (BLLP) mode. -- qcom,mdss-dsi-traffic-mode: Specifies the panel traffic mode. - "non_burst_sync_pulse" = non burst with sync pulses (default). - "non_burst_sync_event" = non burst with sync start event. - "burst_mode" = burst mode. -- qcom,mdss-dsi-pixel-packing: Specifies if pixel packing is used (in case of RGB666). - "tight" = Tight packing (default value). - "loose" = Loose packing. -- qcom,mdss-dsi-virtual-channel-id: Specifies the virtual channel identefier. - 0 = default value. -- qcom,mdss-dsi-color-order: Specifies the R, G and B channel ordering. - "rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value) - "rgb_swap_rbg" = DSI_RGB_SWAP_RBG - "rgb_swap_brg" = DSI_RGB_SWAP_BRG - "rgb_swap_grb" = DSI_RGB_SWAP_GRB - "rgb_swap_gbr" = DSI_RGB_SWAP_GBR -- qcom,mdss-dsi-lane-0-state: Boolean that specifies whether data lane 0 is enabled. -- qcom,mdss-dsi-lane-1-state: Boolean that specifies whether data lane 1 is enabled. -- qcom,mdss-dsi-lane-2-state: Boolean that specifies whether data lane 2 is enabled. -- qcom,mdss-dsi-lane-3-state: Boolean that specifies whether data lane 3 is enabled. -- qcom,mdss-dsi-t-clk-post: Specifies the byte clock cycles after mode switch. - 0x00 = default value. -- qcom,mdss-dsi-t-clk-pre: Specifies the byte clock cycles before mode switch. - 0x00 = default value. -- qcom,mdss-dsi-stream: Specifies the packet stream to be used. - 0 = stream 0 (default) - 1 = stream 1 -- qcom,mdss-dsi-mdp-trigger: Specifies the trigger mechanism to be used for MDP path. - "none" = no trigger - "trigger_te" = Tear check signal line used for trigger - "trigger_sw" = Triggered by software (default) - "trigger_sw_te" = Software trigger and TE -- qcom,mdss-dsi-dma-trigger: Specifies the trigger mechanism to be used for DMA path. - "none" = no trigger - "trigger_te" = Tear check signal line used for trigger - "trigger_sw" = Triggered by software (default) - "trigger_sw_seof" = Software trigger and start/end of frame trigger. - "trigger_sw_te" = Software trigger and TE -- qcom,mdss-dsi-panel-framerate: Specifies the frame rate for the panel. - 60 = 60 frames per second (default) -- qcom,mdss-dsi-panel-clockrate: A 64 bit value specifies the panel clock speed in Hz. - 0 = default value. -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split enabled, this time should not be higher - than two times the dsi link rate time. - 14000 = default value. -- qcom,mdss-dsi-on-command-state: String that specifies the ctrl state for sending ON commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-off-command-state: String that specifies the ctrl state for sending OFF commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-post-mode-switch-on-command-state: String that specifies the ctrl state for sending ON commands post mode switch. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-pan-physical-width-dimension: Specifies panel physical width in mm which corresponds - to the physical width in the framebuffer information. -- qcom,mdss-pan-physical-height-dimension: Specifies panel physical height in mm which corresponds - to the physical height in the framebuffer information. -- qcom,mdss-dsi-panel-test-pin: Specifies the panel test gpio. -- qcom,mdss-dsi-mode-sel-gpio-state: String that specifies the lcd mode for panel - (such as single-port/dual-port), if qcom,panel-mode-gpio - binding is defined in dsi controller. - "dual_port" = Set GPIO to LOW - "single_port" = Set GPIO to HIGH - "high" = Set GPIO to HIGH - "low" = Set GPIO to LOW - The default value is "dual_port". -- qcom,mdss-tear-check-disable: Boolean to disable mdp tear check. Tear check is enabled by default to avoid - tearing. Other tear-check properties are ignored if this property is present. - The below tear check configuration properties can be individually tuned if - tear check is enabled. -- qcom,mdss-tear-check-sync-cfg-height: Specifies the vertical total number of lines. - The default value is 0xfff0. -- qcom,mdss-tear-check-sync-init-val: Specifies the init value at which the read pointer gets loaded - at vsync edge. The reader pointer refers to the line number of - panel buffer that is currently being updated. - The default value is panel height. -- qcom,mdss-tear-check-sync-threshold-start: - Allows the first ROI line write to an panel when read pointer is - between the range of ROI start line and ROI start line plus this - setting. - The default value is 4. -- qcom,mdss-tear-check-sync-threshold-continue: - The minimum number of lines the write pointer needs to be - above the read pointer so that it is safe to write to the panel. - (This check is not done for the first ROI line write of an update) - The default value is 4. -- qcom,mdss-tear-check-start-pos: Specify the y position from which the start_threshold value is - added and write is kicked off if the read pointer falls within that - region. - The default value is panel height. -- qcom,mdss-tear-check-rd-ptr-trigger-intr: - Specify the read pointer value at which an interrupt has to be - generated. - The default value is panel height + 1. -- qcom,mdss-tear-check-frame-rate: Specify the value to be a real frame rate(fps) x 100 factor to tune the - timing of TE simulation with more precision. - The default value is 6000 with 60 fps. -- qcom,mdss-dsi-reset-sequence: An array that lists the - sequence of reset gpio values and sleeps - Each command will have the format defined - as below: - --> Reset GPIO value - --> Sleep value (in ms) -- qcom,partial-update-enabled: String used to enable partial - panel update for command mode panels. - "none": partial update is disabled - "single_roi": default enable mode, only single roi is sent to panel - "dual_roi": two rois are merged into one big roi. Panel ddic should be able - to process two roi's along with the DCS command to send two rois. - disabled if property is not specified. This property is specified - per timing node to support resolution restrictions. -- qcom,mdss-dsi-horizontal-line-idle: List of width ranges (EC - SC) in pixels indicating - additional idle time in dsi clock cycles that is needed - to compensate for smaller line width. -- qcom,partial-update-roi-merge: Boolean indicates roi combination is need - and function has been provided for dcs - 2A/2B command. This property is specified per timing node to support - resolution restrictions. -- qcom,dcs-cmd-by-left: Boolean to indicate that dcs command are sent - through the left DSI controller only in a dual-dsi configuration -- qcom,mdss-dsi-panel-hdr-enabled: Boolean to indicate HDR support in panel. -- qcom,mdss-dsi-panel-hdr-color-primaries: - Array of 8 unsigned integers denoting chromaticity of panel.These - values are specified in nits units. The value range is 0 through 50000. - To obtain real chromacity, these values should be divided by factor of - 50000. The structure of array is defined in below order - value 1: x value of white chromaticity of display panel - value 2: y value of white chromaticity of display panel - value 3: x value of red chromaticity of display panel - value 4: y value of red chromaticity of display panel - value 5: x value of green chromaticity of display panel - value 6: y value of green chromaticity of display panel - value 7: x value of blue chromaticity of display panel - value 8: y value of blue chromaticity of display panel -- qcom,mdss-dsi-panel-peak-brightness: Maximum brightness supported by panel.In absence of maximum value - typical value becomes peak brightness. Value is specified in nits units. - To obtain real peak brightness, this value should be divided by factor of - 10000. -- qcom,mdss-dsi-panel-blackness-level: Blackness level supported by panel. Blackness level is defined as - ratio of peak brightness to contrast. Value is specified in nits units. - To obtain real blackness level, this value should be divided by factor of - 10000. -- qcom,mdss-dsi-lp11-init: Boolean used to enable the DSI clocks and data lanes (low power 11) - before issuing hardware reset line. -- qcom,mdss-dsi-init-delay-us: Delay in microseconds(us) before performing any DSI activity in lp11 - mode. This master delay (t_init_delay as per DSI spec) should be sum - of DSI internal delay to reach fuctional after power up and minimum - delay required by panel to reach functional. -- qcom,mdss-dsi-rx-eot-ignore: Boolean used to enable ignoring end of transmission packets. -- qcom,mdss-dsi-tx-eot-append: Boolean used to enable appending end of transmission packets. -- qcom,ulps-enabled: Boolean to enable support for Ultra Low Power State (ULPS) mode. -- qcom,suspend-ulps-enabled: Boolean to enable support for ULPS mode for panels during suspend state. -- qcom,spr-pack-type: String to specify the SPR pack type of panel pixel layout - Expected string for the pack types supported by MDSS are, - "pentile", "rgbw", "yygm", "yygw" -- qcom,panel-roi-alignment: Specifies the panel ROI alignment restrictions on its - left, top, width, height alignments and minimum width and - height values. This property is specified per timing node to support - resolution's alignment restrictions. -- qcom,esd-check-enabled: Boolean used to enable ESD recovery feature. -- qcom,mdss-dsi-panel-status-command: A byte stream formed by multiple dcs packets based on - qcom dsi controller protocol, to read the panel status. - This value is used to kick in the ESD recovery. - byte 0: dcs data type - byte 1: Unused - byte 2: virtual channel number - byte 3: expect ack from client (dcs read command) - byte 4: wait number of specified ms after dcs command - transmitted - byte 5, 6: 16 bits length in network byte order - byte 7 and beyond: number byte of payload -- qcom,mdss-dsi-panel-status-command-mode: - String that specifies the ctrl state for reading the panel status. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-lp1-command: An optional byte stream to request low - power mode on a panel -- qcom,mdss-dsi-lp1-command-mode: String that specifies the ctrl state for - setting the panel power mode. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-lp2-command: An optional byte stream to request ultra - low power mode on a panel -- qcom,mdss-dsi-lp2-command-mode: String that specifies the ctrl state for - setting the panel power mode. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-nolp-command: An optional byte stream to disable low - power and ultra low power panel modes -- qcom,mdss-dsi-nolp-command-mode: String that specifies the ctrl state for - setting the panel power mode. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-panel-status-check-mode:Specifies the panel status check method for ESD recovery. - "bta_check" = Uses BTA to check the panel status - "reg_read" = Reads panel status register to check the panel status - "reg_read_nt35596" = Reads panel status register to check the panel - status for NT35596 panel. - "te_signal_check" = Uses TE signal behaviour to check the panel status -- qcom,mdss-dsi-panel-status-read-length: Integer array that specify the expected read-back length of values - for each of panel registers. Each length is corresponding to number of - returned parameters of register introduced in specification. -- qcom,mdss-dsi-panel-status-valid-params: Integer array that specify the valid returned values which need to check - for each of register. - Some panel need only check the first few values returned from panel. - So: if this property is the same to qcom,mdss-dsi-panel-status-read-length, - then just ignore this one. -- qcom,mdss-dsi-panel-status-value: Multiple integer arrays, each specifies the values of the panel status register - which is used to check the panel status. The size of each array is the sum of - length specified in qcom,mdss-dsi-panel-status-read-length, and must be equal. - This can cover that Some panel may return several alternative values. -- qcom,mdss-dsi-panel-max-error-count: Integer value that specifies the maximum number of errors from register - read that can be ignored before treating that the panel has gone bad. -- qcom,dynamic-mode-switch-enabled: Boolean used to mention whether panel supports - dynamic switching from video mode to command mode - and vice versa. -- qcom,dynamic-mode-switch-type: A string specifies how to perform dynamic mode switch. - If qcom,dynamic-mode-switch-enabled is set and no string specified, default value is - dynamic-switch-suspend-resume. - "dynamic-switch-suspend-resume"= Switch using suspend/resume. Panel will - go blank during transition. - "dynamic-switch-immediate"= Switch on next frame update. Panel will - not go blank for this transition. - "dynamic-resolution-switch-immediate"= Switch the panel resolution. Panel will - not go blank for this transition. -- qcom,mdss-dsi-post-mode-switch-on-command: Multiple dcs packets used for turning on DSI panel - after panel has switch modes. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,cmd-mode-switch-out-commands: List of commands that need to be sent - to panel in order to switch out command mode dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,cmd-mode-switch-out-commands-state: String that specifies the ctrl state for sending command mode switch out - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,cmd-mode-switch-in-commands: List of commands that need to be sent - to panel in order to switch in command mode dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,cmd-mode-switch-in-commands-state: String that specifies the ctrl state for sending command mode switch in - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,video-mode-switch-out-commands: List of commands that need to be sent - to panel in order to switch out video mode dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,video-mode-switch-out-commands-state: String that specifies the ctrl state for sending video mode switch out - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,video-mode-switch-in-commands: List of commands that need to be sent - to panel in order to switch in video mode dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,video-mode-switch-in-commands-state: String that specifies the ctrl state for sending video mode switch in - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,send-pps-before-switch: Boolean propety to indicate when PPS commands should be sent, - either before or after switch commands during dynamic resolution - switch in DSC panels. If the property is not present, the default - behavior is to send PPS commands after the switch commands. -- qcom,mdss-dsi-panel-orientation: String used to indicate orientation of panel - "180" = panel is flipped in both horizontal and vertical directions - "hflip" = panel is flipped in horizontal direction - "vflip" = panel is flipped in vertical direction -- qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel - for any commands that we send. -- qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always. -- qcom,panel-cphy-mode: Boolean to specify whether panel is using cphy. -- qcom,compression-mode: Select compression mode for panel. - "fbc" - frame buffer compression - "dsc" - display stream compression. - "vdc" - VESA display compression. - If "dsc" or "vdc" compression is used then config subnodes needs to be defined. -- qcom,panel-supply-entries: A node that lists the elements of the supply used to - power the DSI panel. There can be more than one instance - of this binding, in which case the entry would be appended - with the supply entry index. For a detailed description of - fields in the supply entry, refer to the qcom,ctrl-supply-entries - binding above. -- qcom,mdss-dsc-version: An 8 bit value indicates the DSC version supported by panel. Bits[0.3] - provides information about minor version while Bits[4.7] provides - major version information. It supports only DSC rev 1(Major).1(Minor) - right now. -- qcom,mdss-dsc-scr-version: Each DSC version can have multiple SCR. This 8 bit value indicates - current SCR revision information supported by panel. -- qcom,mdss-dsc-encoders: An integer value indicating how many DSC encoders should be used - to drive data stream to DSI. - Default value is 1 and max value is 2. - 2 encoder should be used only if qcom,mdss-lm-split or - qcom,split-mode with pingpong-split is used. -- qcom,mdss-dsc-slice-height: An integer value indicates the dsc slice height. -- qcom,mdss-dsc-slice-width: An integer value indicates the dsc slice width. - Multiple of slice width should be equal to panel-width. - Maximum 2 slices per DSC encoder can be used so if 2 DSC encoders - are used then minimum slice width is equal to panel-width/4. -- qcom,mdss-dsc-slice-per-pkt: An integer value indicates the slice per dsi packet. -- qcom,mdss-dsc-bit-per-component: An integer value indicates the bits per component before compression. -- qcom,mdss-dsc-bit-per-pixel: An integer value indicates the bits per pixel after compression. -- qcom,mdss-dsc-block-prediction-enable: A boolean value to enable/disable the block prediction at decoder. -- qcom,mdss-dsc-config-by-manufacture-cmd: A boolean to indicates panel use manufacture command to setup pps - instead of standard dcs type 0x0A. -- qcom,vdc-version: An 8 bit value indicates the VDC version supported by panel. Bits[0.3] - provides information about minor version while Bits[4.7] provides - major version information. It supports only VDC rev 1(Major).2(Minor) - right now. -- qcom,vdc-version-release: An 8 bit value indicated VDC version release. This has to be set to 0. -- qcom,vdc-slice-height: An u32 value which indicates slice height. This should be at least 16 lines. -- qcom,vdc-slice-width: An u32 value which indicates slice width. This should be at least 64 pixels and - should also be a multiple of 8 -- qcom,vdc-slice-per-pkt: An u32 value indicates the slice per dsi packet. -- qcom,vdc-bit-per-component: An u32 value indicates the bits per component before compression. -- qcom,vdc-bit-per-pixel: An u32 value indicates the bits per pixel after compression. -- qcom,src-color-space: An u32 value indicating the source color space. It can either be RGB or YUV. - Default value is assumed to be RGB - 0 - RGB - 1 - YUV -- qcom,src-chroma-format: An u32 value indicating the source color space. It can either be 444, 420 or 422. - Default value is assumed to be 444 - 0 - 444 - 1 - 422 - 2 - 420 -- qcom,mdss-pps-delay-ms: An u32 value that indicates post PPS command - delay in milliseconds. If no value is specified, it chooses zero by default. -- qcom,display-topology: Array of u32 values which specifies the list of topologies available - for the display. A display topology is defined by a - set of 3 values in the order: - - number of mixers - - number of compression encoders - - number of interfaces - Therefore, the array should always contain a tuple of 3 elements. -- qcom,default-topology-index: An u32 value which indexes the topology set - specified by the node "qcom,display-topology" - to identify the default topology for the - display. The first set is indexed by the - value 0. -- qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. -- qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active - region for video mode panels and line number after TE for command mode - panels, at which command DMA needs to be triggered. -- qcom,mdss-dsi-dma-schedule-window: An integer value indicates the width of the DMA window during which a - DCS command will be triggered for command mode panels -- qcom,mdss-dsi-mdp-idle-ctrl-en: A boolean to enable LP11 insertion after transmission of every line. - This requires command mdp burst mode to be disabled. -- qcom,mdss-dsi-mdp-idle-ctrl-len: An u32 value indicating the number of dsi pclk cycles of idle time - to insert between command mode mdp packets. This time must be long - enough to cover the time link takes to switch between HS to LP11 mode. -- qcom,vert-padding-value: An u32 value indicating the second display height while using two displays - in shared display feature. - -Required properties for sub-nodes: None -Optional properties: -- qcom,dba-panel: Indicates whether the current panel is used as a display bridge - to a non-DSI interface. -- qcom,bridge-name: A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name - is required if qcom,dba-panel is defined for the panel. -- qcom,adjust-timer-wakeup-ms: An integer value to indicate the timer delay(in ms) to accommodate - s/w delay while configuring the event timer wakeup logic. - -- qcom,mdss-dsi-display-timings: Parent node that lists the different resolutions that the panel supports. - Each child represents timings settings for a specific resolution. -- qcom,mdss-dsi-post-init-delay: Specifies required number of frames to wait so that panel can be functional - to show proper display. -- qcom,mdss-dsi-video-mode: A boolean to indicates current timing can only work in video mode. -- qcom,mdss-dsi-cmd-mode: A boolean to indicates current timing can only work in command mode. - -Additional properties added to the second level nodes that represent timings properties: -- qcom,mdss-dsi-timing-default: Property that specifies the current child as the default - timing configuration that will be used. -- qcom,mdss-dsi-timing-switch-command: List of commands that need to be sent - to panel when the resolution/timing switch happens dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,mdss-dsi-timing-switch-command-state: String that specifies the ctrl state for sending resolution switch - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,dsi-dyn-clk-list: An u32 array of all the supported dsi bit clock - frequencies in Hz for the given mode, listed in - order of preference. -- qcom,disable-rsc-solver: Timing node property to dynamically disable RSC solver for - high FPS usecase due to lower bitclk rate. - -Note, if a given optional qcom,* binding is not present, then the driver will configure -the default values specified. - -Example: -&mdss_mdp { - dsi_sim_vid: qcom,mdss_dsi_sim_video { - qcom,mdss-dsi-panel-name = "simulator video mode dsi panel"; - qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-pixel-packing = <0>; - qcom,mdss-dsi-panel-destination = "display_1"; - qcom,cmd-sync-wait-broadcast; - qcom,mdss-dsi-fbc-enable; - qcom,mdss-dsi-panel-mode-switch; - qcom,poms-align-panel-vsync; - qcom,mdss-dsi-bpp-switch; - qcom,mdss-dsi-fbc-slice-height = <5>; - qcom,mdss-dsi-fbc-2d-pred-mode; - qcom,mdss-dsi-fbc-ver2-mode; - qcom,mdss-dsi-fbc-bpp = <0>; - qcom,mdss-dsi-fbc-packing = <0>; - qcom,mdss-dsi-fbc-quant-error; - qcom,mdss-dsi-fbc-bias = <0>; - qcom,mdss-dsi-fbc-pat-mode; - qcom,mdss-dsi-fbc-vlc-mode; - qcom,mdss-dsi-fbc-bflc-mode; - qcom,mdss-dsi-fbc-h-line-budget = <0>; - qcom,mdss-dsi-fbc-budget-ctrl = <0>; - qcom,mdss-dsi-fbc-block-budget = <0>; - qcom,mdss-dsi-fbc-lossless-threshold = <0>; - qcom,mdss-dsi-fbc-lossy-threshold = <0>; - qcom,mdss-dsi-fbc-rgb-threshold = <0>; - qcom,mdss-dsi-fbc-lossy-mode-idx = <0>; - qcom,mdss-dsi-fbc-max-pred-err = <2>; - qcom,mdss-dsi-h-front-porch = <140>; - qcom,mdss-dsi-h-back-porch = <164>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <6>; - qcom,mdss-dsi-v-front-porch = <1>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = < 15>; - qcom,mdss-brightness-max-level = <255>; - qcom,bl-update-flag = "delay_until_first_frame"; - qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-interleave-mode = <0>; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-wd; - qcom,mdss-dsi-te-using-te-pin; - qcom,qsync-enable; - qcom,mdss-dsi-qsync-min-refresh-rate = <30>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-h-sync-pulse = <1>; - qcom,mdss-dsi-hfp-power-mode; - qcom,mdss-dsi-hbp-power-mode; - qcom,mdss-dsi-hsa-power-mode; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-last-line-interleave; - qcom,mdss-dsi-traffic-mode = <0>; - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-color-order = <0>; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-t-clk-post = <0x20>; - qcom,mdss-dsi-t-clk-pre = <0x2c>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-mdp-trigger = <0>; - qcom,mdss-dsi-dma-trigger = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 - 22 27 1e 03 04 00]; - qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 - 23 20 06 09 05 03 04 a0 - 23 20 06 09 05 03 04 a0 - 23 20 06 09 05 03 04 a0 - 23 2e 06 08 05 03 04 a0]; - qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00 - 29 01 00 00 10 00 02 FF 99]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [22 01 00 00 00 00 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; - qcom,dsi-supported-dfps-list = <30 45 60>; - qcom,dsi-supported-qsync-min-fps-list = <30 40 55>; - qcom,dsi-qsync-avr-step-list = <0 360 660>; - qcom,dsi-qsync-avr-step-fps = <360>; - qcom,min-refresh-rate = <30>; - qcom,max-refresh-rate = <60>; - qcom,mdss-dsi-bl-pmic-bank-select = <0>; - qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>; - qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>; - qcom,5v-boost-gpio = <&pm8994_gpios 14 0>; - qcom,mdss-pan-physical-width-dimension = <60>; - qcom,mdss-pan-physical-height-dimension = <140>; - qcom,mdss-dsi-mode-sel-gpio-state = "dsc_mode"; - qcom,mdss-tear-check-sync-cfg-height = <0xfff0>; - qcom,mdss-tear-check-sync-init-val = <1280>; - qcom,mdss-tear-check-sync-threshold-start = <4>; - qcom,mdss-tear-check-sync-threshold-continue = <4>; - qcom,mdss-tear-check-start-pos = <1280>; - qcom,mdss-tear-check-rd-ptr-trigger-intr = <1281>; - qcom,mdss-tear-check-frame-rate = <6000>; - qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>; - qcom,dcs-cmd-by-left; - qcom,mdss-dsi-lp11-init; - qcom,mdss-dsi-init-delay-us = <100>; - mdss-dsi-rx-eot-ignore; - mdss-dsi-tx-eot-append; - qcom,ulps-enabled; - qcom,suspend-ulps-enabled; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-read-length = <8>; - qcom,mdss-dsi-panel-max-error-count = <3>; - qcom,mdss-dsi-panel-status-value = <0x1c 0x00 0x05 0x02 0x40 0x84 0x06 0x01>; - qcom,dynamic-mode-switch-enabled; - qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; - qcom,mdss-dsi-post-mode-switch-on-command = [32 01 00 00 00 00 02 00 00 - 29 01 00 00 10 00 02 B0 03]; - qcom,video-to-cmd-mode-switch-commands = [15 01 00 00 00 00 02 C2 0B - 15 01 00 00 00 00 02 C2 08]; - qcom,cmd-to-video-mode-switch-commands = [15 01 00 00 00 00 02 C2 03]; - qcom,send-pps-before-switch; - qcom,panel-ack-disabled; - qcom,mdss-dsi-horizontal-line-idle = <0 40 256>, - <40 120 128>, - <128 240 64>; - qcom,mdss-dsi-panel-orientation = "180" - qcom,mdss-dsi-panel-jitter = <0x8 0x10>; - qcom,mdss-dsi-panel-prefill-lines = <0x10>; - qcom,mdss-dsi-force-clock-lane-hs; - qcom,compression-mode = "dsc"; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,platform-reset-gpio = <&tlmm 0 0>; - - qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; - - qcom,mdss-dsi-display-timings { - wqhd { - cell-index = <0>; - qcom,mdss-dsi-cmd-mode; - qcom,mdss-dsi-video-mode; - qcom,mdss-dsi-bpp-mode = <24>; - qcom,mdss-dsi-timing-default; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <8>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <728>; - qcom,mdss-dsi-v-pulse-width = <4>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-clockrate = <424000000>; - qcom,mdss-mdp-transfer-time-us = <12500>; - qcom,dsi-wd-jitter-enable; - qcom,mdss-dsi-panel-jitter = <0x2 0x1>; - qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; - qcom,dsi-wd-ltj-time-sec = <3600>; - qcom,mdss-mdp-transfer-time-us-min = <10000>; - qcom,mdss-mdp-transfer-time-us-max = <15000>; - qcom,mdss-dsi-panel-timings = [E6 38 26 00 68 6E 2A 3C 2C 03 04 00]; - qcom,mdss-dsi-t-clk-post = <0x02>; - qcom,mdss-dsi-t-clk-pre = <0x2a>; - qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00 - 05 01 00 00 02 00 02 29 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-timing-switch-command = [ - 29 00 00 00 00 00 02 B0 04 - 29 00 00 00 00 00 02 F1 00]; - qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; - qcom,qsync-mode-min-refresh-rate = <48>; - qcom,dsi-qsync-mode-avr-step-fps = <360>; - qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; - qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; - qcom,video-mode-switch-out-commands = [ - 39 01 00 00 00 00 06 b2 00 5d 04 80 49]; - qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; - qcom,video-mode-switch-in-commands = [ - 39 01 00 00 00 00 06 b2 00 5d 04 80 40]; - qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; - qcom,cmd-mode-switch-in-commands = [ - 39 01 00 00 00 00 06 b2 00 5d 04 80 42]; - qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; - qcom,cmd-mode-switch-out-commands = [ - 39 01 00 00 00 00 06 b2 00 5d 01 02 50]; - qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; - - qcom,dsi-dyn-clk-list = <524637388 525735938 528842882>; - - qcom,vert-padding-value = <2940>; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - qcom,mdss-dsc-config-by-manufacture-cmd; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <4 4 2 2 20 20>; - }; - }; - qcom,panel-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <2800000>; - qcom,supply-max-voltage = <2800000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <0>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <0>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - }; - - qcom,dba-panel; - qcom,bridge-name = "adv7533"; - qcom,mdss-dsc-version = <0x11>; - qcom,mdss-dsc-scr-version = <0x1>; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - qcom,mdss-dsc-config-by-manufacture-cmd; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <0>; - qcom,vdc-version = <0x12>; - qcom,vdc-version-release = <0>; - qcom,vdc-slice-height = <256>; - qcom,vdc-slice-width = <720>; - qcom,vdc-slice-per-pkt = <2>; - qcom,vdc-bit-per-component = <8>; - qcom,vdc-bit-per-pixel = <6>; - qcom,src-color-space = <0>; - qcom,src-chroma-format = <0>; - qcom,mdss-dsi-dma-schedule-line = <5>; - qcom,mdss-dsi-dma-schedule-window = <50>; - }; -}; diff --git a/bindings/mdss-dsi-panel.yaml b/bindings/mdss-dsi-panel.yaml new file mode 100644 index 00000000..54e88f3a --- /dev/null +++ b/bindings/mdss-dsi-panel.yaml @@ -0,0 +1,1923 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mdss-dsi-panel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QTI mdss-dsi-panel + +description: > + mdss-dsi-panel is a dsi panel device which supports panels that + are compatible with MIPI display serial interface specification. + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +properties: + compatible: + description: > + This property applies to DSI V2 panels only. + This property should not be added for panels + that work based on version "V6.0" + DSI panels that are of different versions + are initialized by the drivers for dsi controller. + This property specifies the version + for DSI HW that this panel will work with + "qcom,dsi-panel-v2" = DSI V2.0 + + status: + description: > + This property applies to DSI V2 panels only. + This property should not be added for panels + that work based on version "V6.0" + DSI panels that are of different versions + are initialized by the drivers for dsi controller. + A string that has to be set to "okay/ok" + to enable the panel driver. By default this property + will be set to "disable". Will be set to "ok/okay" + status for specific platforms. + default: disable + + qcom,mdss-dsi-panel-controller: + description: > + Specifies the phandle for the DSI controller that + this panel will be mapped to. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,mdss-dsi-panel-width: + description: Specifies panel width in pixels. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-height: + description: Specifies panel height in pixels. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-bpp: + description: > + Specifies the panel bits per pixel. + 3 = for rgb111 + 8 = for rgb332 + 12 = for rgb444 + 16 = for rgb565 + 18 = for rgb666 + 24 = for rgb888 + enum: [3, 8, 12, 16, 18, 24] + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-destination: + description: > + A string that specifies the destination display for the panel. + "display_1" = DISPLAY_1 + "display_2" = DISPLAY_2 + $ref: /schemas/types.yaml#/definitions/string-array + enum: [display_1, display_2] + + qcom,mdss-dsi-panel-timings: + description: > + An array of length 12 that specifies the PHY timing settings for + the panel. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 12 + maxItems: 12 + + qcom,mdss-dsi-panel-timings-8996: + description: > + An array of length 40 char that specifies the 8996 PHY lane + timing settings for the panel. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 40 + maxItems: 40 + + qcom,mdss-dsi-on-command: + description: > + A byte stream formed by multiple dcs packets base on + qcom dsi controller protocol. + byte 0: dcs data type + byte 1: Unused + byte 2: virtual channel number + byte 3: Message flags + byte 4: wait number of specified ms after dcs command transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload + Note, if a short DCS packet(i.e packet with Byte 0:dcs data type as 05) mentioned in + qcom,mdss-dsi-on-command/qcom,mdss-dsi-off-command stream fails to transmit, + then 3 options can be tried. + 1. Send the packet as a long packet instead + Byte 0: dcs data type = 05 (DCS short Packet) + Byte 0: dcs data type = 29 (DCS long Packet) + 2. Send the packet in one burst by prepending with the next packet in packet stream + Byte 3 = 00 (indicates this is an individual packet) + Byte 3 = 40 (indicates this will be appended to the next + individual packet in the packet stream) + 3. Prepend a NULL packet to the short packet and send both in one burst instead of + combining multiple short packets and sending them in one burst. + + qcom,mdss-dsi-off-command: + description: > + A byte stream formed by multiple dcs packets based on + qcom dsi controller protocol. + Refer to qcom,mdss-dsi-on-command for command format. + + qcom,mdss-dsi-post-panel-on-command: + description: > + same as "qcom,mdss-dsi-on-command" except commands are + sent after displaying an image. + + qcom,platform-reset-gpio: + description: > + Specifies the reset gpio of primary display, not required for simulation + panels. + + cell-index: + description: Timing node index to help driver maintain the device tree ordering. + + qcom,platform-sec-reset-gpio: + description: Specifies the reset gpio of secondary display. + + qcom,platform-bklight-en-gpio: + description: Specifies the gpio for enabling backlight. + + qcom,mdss-dsi-panel-name: + description: A string used as a descriptive name of the panel + + qcom,vid-on-commands: + description: > + same as "qcom,mdss-dsi-on-command" except commands are + only sent for video mode. + + qcom,vid-on-commands-state: + description: > + String that specifies the ctrl state for sending panel on commands. + for video mode. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + default: dsi_lp_mode + + qcom,cmd-on-commands: + description: > + same as "qcom,mdss-dsi-on-command" except commands are + only sent for command mode. + + qcom,cmd-on-commands-state: + description: > + String that specifies the ctrl state for sending panel on commands. + for command mode. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + + qcom,mdss-dsi-physical-type: + description: > + A string used as a decriptive type of the panel. + "oled" : That indicate it's an OLED panel. + "lcd" : That indicate it's an LCD panel. + If it is not set, consider it is a LCD panel as default. + default: lcd + enum: [oled, lcd] + + qcom,mdss-dsi-panel-phy-timings: + description: > + An array of length 'n' char that specifies the DSI PHY lane + timing settings for the panel. This is specific to SDE DRM driver. + The value of 'n' depends on the DSI PHY h/w revision and parsing this + property properly will be taken care in the DSI PHY DRM driver. + + qcom,cmd-sync-wait-broadcast: + description: Boolean used to broadcast dcs command to panels. + + qcom,mdss-dsi-fbc-enable: + description: Boolean used to enable frame buffer compression mode. + + qcom,mdss-dsi-panel-mode-switch: + description: Boolean used to enable panel operating mode switch. + + qcom,poms-align-panel-vsync: + description: Boolean used to align panel TE with timing engine vsync in POMS + + qcom,mdss-dsi-bpp-switch: + description: Boolean used to enable bpp mode switch for non-DSC modes. + + qcom,mdss-dsi-bpp-mode: + description: > + Specifies the panel bits per pixel per timing node, only used when "qcom,mdss-dsi-bpp-switch" + is set. + 24 = for rgb888, default mode if "qcom,mdss-dsi-bpp-mode" is not set. + 30 = for rgb101010. + enum: [24, 30] + + qcom,mdss-dsi-fbc-slice-height: + description: > + Slice height(in lines) of compressed block. + Expressed as power of 2. To set as 128 lines, + this should be set to 7. + + qcom,mdss-dsi-fbc-2d-pred-mode: + description: Boolean to enable 2D map prediction. + + qcom,mdss-dsi-fbc-ver2-mode: + description: Boolean to enable FBC 2.0 that supports 1/3 compression. + + qcom,mdss-dsi-fbc-bpp: + description: > + Compressed bpp supported by the panel. + Specified color order is used as default value. + + qcom,mdss-dsi-fbc-packing: + description: Component packing. 0 = default value. + default: 0 + + qcom,mdss-dsi-fbc-quant-error: + description: Boolean used to enable quantization error calculation. + + qcom,mdss-dsi-fbc-bias: + description: > + Bias for CD. + 0 = default value. + default: 0 + + qcom,mdss-dsi-fbc-pat-mode: + description: Boolean used to enable PAT mode. + + qcom,mdss-dsi-fbc-vlc-mode: + description: Boolean used to enable VLC mode. + + qcom,mdss-dsi-fbc-bflc-mode: + description: Boolean used to enable BFLC mode. + + qcom,mdss-dsi-fbc-h-line-budget: + description: > + Per line extra budget. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-budget-ctrl: + description: > + Extra budget level. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-block-budget: + description: Per block budget. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-lossless-threshold: + description: > + Lossless mode threshold. + 0 = default value.. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-lossy-threshold: + description: > + Lossy mode threshold. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-rgb-threshold: + description: > + Lossy RGB threshold. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-lossy-mode-idx: + description: > + Lossy mode index value. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-max-pred-err: + description: > + Max quantization prediction error. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-back-porch: + description: > + Horizontal back porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-front-porch: + description: > + Horizontal front porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-pulse-width: + description: > + Horizontal pulse width. + 2 = default value. + default: 2 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-sync-skew: + description: > + Horizontal sync skew value. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-back-porch: + description: > + Vertical back porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-front-porch: + description: > + Vertical front porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-pulse-width: + description: > + Vertical pulse width. + 2 = default value. + default: 2 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-left-border: + description: > + Horizontal left border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-right-border: + description: > + Horizontal right border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-top-border: + description: > + Vertical top border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-bottom-border: + description: > + Vertical bottom border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-underflow-color: + description: > + Specifies the controller settings for the + panel under flow color. + 0xff = default value. + default: 0xff + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-border-color: + description: > + Defines the border color value if border is present. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-jitter: + description: > + Panel jitter value is expressed in terms of numerator + and denominator. It contains two u32 values - numerator + followed by denominator. The jitter configurition causes + the early wakeup if panel needs to adjust before vsync. + Default jitter value is 2.0%. Max allowed value is 10%. + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 2 + minItems: 2 + items: + - description: numerator of jitter configuration + - description: denominator of jitter configuration + + qcom,dsi-wd-jitter-enable: + description: Boolean used to enable watchdog jitter in simulator panels + + qcom,dsi-wd-ltj-max-jitter: + description: > + A u32 pair with numerator and denominator specifying the + maximum jitter over a long time. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + + qcom,dsi-wd-ltj-time-sec: + description: A u32 value to specify the time over which the jitter increases. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-prefill-lines: + description: > + An integer value defines the panel prefill lines required to + calculate the backoff time of rsc. + Default value is 16 lines. Max allowed value is vtotal. + default: 16 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-pan-enable-dynamic-fps: + description: Boolean used to enable change in frame rate dynamically. + + qcom,mdss-dsi-pan-fps-update: + description: > + A string that specifies when to change the frame rate. + "dfps_suspend_resume_mode"= FPS change request is + implemented during suspend/resume. + "dfps_immediate_clk_mode" = FPS change request is + implemented immediately using DSI clocks. + "dfps_immediate_porch_mode_hfp" = FPS change request is + implemented immediately by changing panel horizontal + front porch values. + "dfps_immediate_porch_mode_vfp" = FPS change request is + implemented immediately by changing panel vertical + front porch values. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,dsi-supported-dfps-list: + description: List containing all the supported refresh rates. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,dsi-supported-qsync-min-fps-list: + description: > + The fps value in this list indicates the qsync min fps + corresponding to the mode in the qcom,dsi-supported-dfps-list with same index. + qcom,dsi-supported-qsync-min-fps-list cannot be defined along with + qcom,mdss-dsi-qsync-min-refresh-rate. "qcom,qsync-enable" property should be + set along with this property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,qsync-mode-min-refresh-rate: + description: > + This u32 property is used to define qsync min fps per timing node instead + of using same qsync min fps for different timing modes. For defining qsync min + fps per timing node, this property should be defined in all timing nodes or else + to define single qsync fps for all modes, + "qcom,mdss-dsi-qsync-min-refresh-rate" property can be used. + "qcom,qsync-enable" property should be set along with this property. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-qsync-avr-step-list: + description: > + The u32 fps values in this optional list indicate the avr step + requirement for qsync/AVR video mode panels. When a late frame is triggered, + AVR will delay the trigger to ensure the frame transfer snaps to the next step + interval. The step rate must be a common multiple of refresh and min-fps rates. + The values in this list should correspond to the dfps-list with same indeces + when DFPS is used, or a single value which applies to all rates. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-qsync-mode-avr-step-fps: + description: > + This u32 property is used to define avr step fps per timing node instead + of using same qsync avr step fps for different timing modes. + For defining avr step fps per timing node, this property should be defined + in all timing nodes or else to define single qsync avr step fps for all modes + use "qcom,mdss-dsi-qsync-avr-step-fps". + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-qsync-avr-step-fps: + description: > + A u32 entry to specify avr step rate supported by the panel. + "qcom,qsync-enable" property should be set along with this property + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-transfer-time-us-min: + description: > + Minimum supported mdp transfer time in us. This entry enables support to + dynamically set the transfer time for the given mode within the defined + range. Both min & max must be defined to enable. + qcom,mdss-dsi-transfer-time-us must be greater than this value. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-transfer-time-us-max: + description: > + Maximum supported mdp transfer time in us. This entry enables support to + dynamically set the transfer time for the given mode within the defined + range. Both min & max must be defined to enable. This time should not be + greater than vsync duration. + qcom,mdss-dsi-transfer-time-us must be less than this value. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,min-refresh-rate: + description: Minimum refresh rate supported by the panel. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,max-refresh-rate: + description: > + Maximum refresh rate supported by the panel. If max refresh + rate is not specified, then the frame rate of the panel in + qcom,mdss-dsi-panel-framerate is used. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-dyn-clk-enable: + description: > + Boolean to indicate dsi dynamic clock switch feature + is supported. + + qcom,dsi-dyn-clk-type: + description: > + A string that specifies the sub-type for the dynamic + clk feature. If dyn clk type is not specified, default + value "legacy" is used. + "legacy" = FPS is not maintained after dynamic clock switch. + "constant-fps-adjust-hfp" = FPS is maintained even after + dynamic clock switch by changing panel horizontal front + porch values. + "constant-fps-adjust-vfp" = FPS is maintained even after + dynamic clock switch by changing panel vertical front + porch values. + This dyn-clk-type entry is an optional binding which is + contingent on the enabling of dynamic clock switch. + $ref: /schemas/types.yaml#/definitions/string-array + default: legacy + + qcom,mdss-dsi-bl-pmic-control-type: + description: > + A string that specifies the implementation of backlight + control for this panel. + "bl_ctrl_pwm" = Backlight controlled by PWM gpio. + "bl_ctrl_wled" = Backlight controlled by WLED. + "bl_ctrl_dcs" = Backlight controlled by DCS commands. + "bl_ctrl_external" = Backlight controlled by externally + other: Unknown backlight control. (default) + $ref: /schemas/types.yaml#/definitions/string-array + default: other + + qcom,mdss-dsi-sec-bl-pmic-control-type: + description: > + A string that specifies the implementation of backlight + control for secondary panel. + "bl_ctrl_pwm" = Backlight controlled by PWM gpio. + "bl_ctrl_wled" = Backlight controlled by WLED. + "bl_ctrl_dcs" = Backlight controlled by DCS commands. + "bl_ctrl_external" = Backlight controlled by externally + other: Unknown backlight control. (default) + $ref: /schemas/types.yaml#/definitions/string-array + default: other + + qcom,mdss-dsi-bl-pwm-pmi: + description: Boolean to indicate that PWM control is through second pmic chip. + + qcom,mdss-dsi-bl-pmic-bank-select: + description: > + LPG channel for backlight. + Required if backlight pmic control type is PWM + + qcom,mdss-dsi-bl-pmic-pwm-frequency: + description: > + PWM period in microseconds. + Required if backlight pmic control type is PWM + + qcom,mdss-dsi-pwm-gpio: + description: > + PMIC gpio binding to backlight. + Required if backlight pmic control type is PWM + + qcom,mdss-dsi-bl-min-level: + description: > + Specifies the min backlight level supported by the panel. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-bl-max-level: + description: > + Specifies the max backlight level supported by the panel. + 255 = default value. + default: 255 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-bl-inverted-dbv: + description: > + A boolean to specify whether to invert the display brightness value. + When this boolean is set, will inverted display brightness value. + + qcom,bl-dsc-cmd-state: + description: > + String that specifies the ctrl state for sending dcs brightness commands. + "dsi_hs_mode" = DSI high speed mode (default) + "dsi_lp_mode" = DSI low power mode + If the string was not set, dsi_hs_mode will be set as default mode. + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_hs_mode + enum: [dsi_hs_mode, dsi_lp_mode] + + qcom,mdss-brightness-max-level: + description: > + Specifies the max brightness level supported. + 255 = default value. + default: 255 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,bl-update-flag: + description: > + A string that specifies controls for backlight update of the panel. + "delay_until_first_frame" = Delay backlight update of the panel + until the first frame is received from the HW. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-interleave-mode: + description: > + Specifies interleave mode. + 0 = default value. + default: 0 + + qcom,mdss-dsi-panel-type: + description: > + Specifies the panel operating mode. + "dsi_video_mode" = enable video mode (default). + "dsi_cmd_mode" = enable command mode. + default: dsi_video_mode + + qcom,5v-boost-gpio: + description: Specifies the panel gpio for display 5v boost. + + qcom,mdss-dsi-te-check-enable: + description: Boolean to enable Tear Check configuration. + + qcom,mdss-dsi-te-using-wd: + description: > + Boolean entry enables the watchdog timer support to generate the vsync signal + for command mode panel. By default, panel TE will be used to generate the vsync. + + qcom,mdss-dsi-te-using-te-pin: + description: Boolean to specify whether using hardware vsync. + + qcom,qsync-enable: + description: Boolean property to indicate if qsync is enabled/disabled. + + qcom,mdss-dsi-qsync-min-refresh-rate: + description: > + A u32 entry to specify minimum refresh rate supported by the panel to enable qsync feature. + "qcom,qsync-enable" property should be set along with this property. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-qsync-on-commands: + description: String that specifies the commands to enable qsync feature. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-qsync-on-commands-state: + description: > + String that specifies the ctrl state for sending qsync on commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-qsync-off-commands: + description: String that specifies the commands to disable qsync feature. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-qsync-off-commands-state: + description: > + String that specifies the ctrl state for sending qsync off commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-te-pin-select: + description: > + Specifies TE operating mode. + 0 = TE through embedded dcs command + 1 = TE through TE gpio pin. (default) + default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,mdss-dsi-te-dcs-command: + description: > + Inserts the dcs command. + 1 = default value. + default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-wr-mem-start: + description: > + DCS command for write_memory_start. + 0x2c = default value. + default: 0x2c + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-wr-mem-continue: + description: > + DCS command for write_memory_continue. + 0x3c = default value. + default: 0x3c + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-sync-pulse: + description: > + Specifies the pulse mode option for the panel. + 0 = Don't send hsa/he following vs/ve packet(default) + 1 = Send hsa/he following vs/ve packet + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,mdss-dsi-hfp-power-mode: + description: > + Boolean to determine DSI lane state during + horizontal front porch (HFP) blanking period. + + qcom,mdss-dsi-hbp-power-mode: + description: > + Boolean to determine DSI lane state during + horizontal back porch (HBP) blanking period. + + qcom,mdss-dsi-hsa-power-mode: + description: > + Boolean to determine DSI lane state during + horizontal sync active (HSA) mode. + + qcom,mdss-dsi-last-line-interleave: + description: > + Boolean to determine if last line + interleave flag needs to be enabled. + + qcom,mdss-dsi-bllp-eof-power-mode: + description: > + Boolean to determine DSI lane state during + blanking low power period (BLLP) EOF mode. + + qcom,mdss-dsi-bllp-power-mode: + description: > + Boolean to determine DSI lane state during + blanking low power period (BLLP) mode. + + qcom,mdss-dsi-traffic-mode: + description: > + Specifies the panel traffic mode. + "non_burst_sync_pulse" = non burst with sync pulses (default). + "non_burst_sync_event" = non burst with sync start event. + "burst_mode" = burst mode. + default: non_burst_sync_pulse + enum: [non_burst_sync_pulse, non_burst_sync_event, burst_mode] + + qcom,mdss-dsi-pixel-packing: + description: > + Specifies if pixel packing is used (in case of RGB666). + "tight" = Tight packing (default value). + "loose" = Loose packing. + default: tight + enum: [tight, loose] + + qcom,mdss-dsi-virtual-channel-id: + description: > + Specifies the virtual channel identefier. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-color-order: + description: > + Specifies the R, G and B channel ordering. + "rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value) + "rgb_swap_rbg" = DSI_RGB_SWAP_RBG + "rgb_swap_brg" = DSI_RGB_SWAP_BRG + "rgb_swap_grb" = DSI_RGB_SWAP_GRB + "rgb_swap_gbr" = DSI_RGB_SWAP_GBR + default: rgb_swap_rgb + enum: [rgb_swap_rgb, rgb_swap_rbg, rgb_swap_brg, rgb_swap_grb, rgb_swap_gbr] + + qcom,mdss-dsi-lane-0-state: + description: Boolean that specifies whether data lane 0 is enabled. + + qcom,mdss-dsi-lane-1-state: + description: Boolean that specifies whether data lane 1 is enabled. + + qcom,mdss-dsi-lane-2-state: + description: Boolean that specifies whether data lane 2 is enabled. + + qcom,mdss-dsi-lane-3-state: + description: Boolean that specifies whether data lane 3 is enabled. + + qcom,mdss-dsi-t-clk-post: + description: > + Specifies the byte clock cycles after mode switch. + 0x00 = default value. + default: 0x00 + + qcom,mdss-dsi-t-clk-pre: + description: > + Specifies the byte clock cycles before mode switch. + 0x00 = default value. + default: 0x00 + + qcom,mdss-dsi-stream: + description: > + Specifies the packet stream to be used. + 0 = stream 0 (default) + 1 = stream 1 + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,mdss-dsi-mdp-trigger: + description: > + Specifies the trigger mechanism to be used for MDP path. + "none" = no trigger + "trigger_te" = Tear check signal line used for trigger + "trigger_sw" = Triggered by software (default) + "trigger_sw_te" = Software trigger and TE + $ref: /schemas/types.yaml#/definitions/string-array + default: trigger_sw + enum: [none, trigger_te, trigger_sw, trigger_sw_te] + + qcom,mdss-dsi-dma-trigger: + description: > + Specifies the trigger mechanism to be used for DMA path. + "none" = no trigger + "trigger_te" = Tear check signal line used for trigger + "trigger_sw" = Triggered by software (default) + "trigger_sw_seof" = Software trigger and start/end of frame trigger. + "trigger_sw_te" = Software trigger and TE + $ref: /schemas/types.yaml#/definitions/string-array + default: trigger_sw + enum: [none, trigger_te, trigger_sw, trigger_sw_seof, trigger_sw_te] + + qcom,mdss-dsi-panel-framerate: + description: > + Specifies the frame rate for the panel. + 60 = 60 frames per second (default) + default: 60 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-clockrate: + description: > + A 64 bit value specifies the panel clock speed in Hz. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint64 + + qcom,mdss-mdp-transfer-time-us: + description: > + Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split enabled, this time should not be higher + than two times the dsi link rate time. + 14000 = default value. + default: 14000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-on-command-state: + description: > + String that specifies the ctrl state for sending ON commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-off-command-state: + description: > + String that specifies the ctrl state for sending OFF commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-post-mode-switch-on-command-state: + description: > + String that specifies the ctrl state for sending ON commands post mode switch. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-pan-physical-width-dimension: + description: > + Specifies panel physical width in mm which corresponds + to the physical width in the framebuffer information. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-pan-physical-height-dimension: + description: > + Specifies panel physical height in mm which corresponds + to the physical height in the framebuffer information. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-test-pin: + description: Specifies the panel test gpio. + + qcom,mdss-dsi-mode-sel-gpio-state: + description: > + String that specifies the lcd mode for panel + (such as single-port/dual-port), if qcom,panel-mode-gpio + binding is defined in dsi controller. + "dual_port" = Set GPIO to LOW + "single_port" = Set GPIO to HIGH + "high" = Set GPIO to HIGH + "low" = Set GPIO to LOW + The default value is "dual_port". + $ref: /schemas/types.yaml#/definitions/string-array + default: dual_port + enum: [dual_port, single_port, high, low] + + qcom,mdss-tear-check-disable: + description: > + Boolean to disable mdp tear check. Tear check is enabled by default to avoid + tearing. Other tear-check properties are ignored if this property is present. + The below tear check configuration properties can be individually tuned if + tear check is enabled. + + qcom,mdss-tear-check-sync-cfg-height: + description: > + Specifies the vertical total number of lines. + The default value is 0xfff0. + default: 0xfff0 + + qcom,mdss-tear-check-sync-init-val: + description: > + Specifies the init value at which the read pointer gets loaded + at vsync edge. The reader pointer refers to the line number of + panel buffer that is currently being updated. + The default value is panel height. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-sync-threshold-start: + description: > + Allows the first ROI line write to an panel when read pointer is + between the range of ROI start line and ROI start line plus this + setting. + The default value is 4. + default: 4 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-sync-threshold-continue: + description: > + The minimum number of lines the write pointer needs to be + above the read pointer so that it is safe to write to the panel. + (This check is not done for the first ROI line write of an update) + The default value is 4. + default: 4 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-start-pos: + description: > + Specify the y position from which the start_threshold value is + added and write is kicked off if the read pointer falls within that + region. + The default value is panel height. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-rd-ptr-trigger-intr: + description: > + Specify the read pointer value at which an interrupt has to be + generated. + The default value is panel height + 1. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-frame-rate: + description: > + Specify the value to be a real frame rate(fps) x 100 factor to tune the + timing of TE simulation with more precision. + The default value is 6000 with 60 fps. + $ref: /schemas/types.yaml#/definitions/uint32 + + qqcom,mdss-dsi-reset-sequence: + description: > + An array that lists the + sequence of reset gpio values and sleeps + Each command will have the format defined + as below: + --> Reset GPIO value + --> Sleep value (in ms) + + qcom,partial-update-enabled: + description: > + String used to enable partial + panel update for command mode panels. + "none": partial update is disabled + "single_roi": default enable mode, only single roi is sent to panel + "dual_roi": two rois are merged into one big roi. Panel ddic should be able + to process two roi's along with the DCS command to send two rois. + disabled if property is not specified. This property is specified + per timing node to support resolution restrictions. + $ref: /schemas/types.yaml#/definitions/string-array + default: single_roi + enum: [none, single_roi, dual_roi] + + qcom,mdss-dsi-horizontal-line-idle: + description: > + List of width ranges (EC - SC) in pixels indicating + additional idle time in dsi clock cycles that is needed + to compensate for smaller line width. + + qcom,partial-update-roi-merge: + description: > + Boolean indicates roi combination is need + and function has been provided for dcs + 2A/2B command. This property is specified per timing node to support + resolution restrictions. + + qcom,dcs-cmd-by-left: + description: > + Boolean to indicate that dcs command are sent + through the left DSI controller only in a dual-dsi configuration + + qcom,mdss-dsi-panel-hdr-enabled: + description: > + Boolean to indicate HDR support in panel. + + qcom,mdss-dsi-panel-hdr-color-primaries: + description: > + Array of 8 unsigned integers denoting chromaticity of panel.These + values are specified in nits units. The value range is 0 through 50000. + To obtain real chromacity, these values should be divided by factor of + 50000. The structure of array is defined in below order + value 1: x value of white chromaticity of display panel + value 2: y value of white chromaticity of display panel + value 3: x value of red chromaticity of display panel + value 4: y value of red chromaticity of display panel + value 5: x value of green chromaticity of display panel + value 6: y value of green chromaticity of display panel + value 7: x value of blue chromaticity of display panel + value 8: y value of blue chromaticity of display panel + $ref: /schemas/types.yaml#/definitions/uint32-array + minimum: 0 + maximum: 50000 + items: + - description: x value of white chromaticity of display panel + - description: y value of white chromaticity of display panel + - description: x value of red chromaticity of display panel + - description: y value of red chromaticity of display panel + - description: x value of green chromaticity of display panel + - description: y value of green chromaticity of display panel + - description: x value of blue chromaticity of display panel + - description: y value of blue chromaticity of display panel + + qcom,mdss-dsi-panel-peak-brightness: + description: > + Maximum brightness supported by panel.In absence of maximum value + typical value becomes peak brightness. Value is specified in nits units. + To obtain real peak brightness, this value should be divided by factor of + 10000. + + qcom,mdss-dsi-panel-blackness-level: + description: > + Blackness level supported by panel. Blackness level is defined as + ratio of peak brightness to contrast. Value is specified in nits units. + To obtain real blackness level, this value should be divided by factor of + 10000. + + qcom,mdss-dsi-lp11-init: + description: > + Boolean used to enable the DSI clocks and data lanes (low power 11) + before issuing hardware reset line. + + qcom,mdss-dsi-init-delay-us: + description: > + Delay in microseconds(us) before performing any DSI activity in lp11 + mode. This master delay (t_init_delay as per DSI spec) should be sum + of DSI internal delay to reach fuctional after power up and minimum + delay required by panel to reach functional. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-rx-eot-ignore: + description: Boolean used to enable ignoring end of transmission packets. + + qcom,mdss-dsi-tx-eot-append: + description: Boolean used to enable appending end of transmission packets. + + qcom,ulps-enabled: + description: Boolean to enable support for Ultra Low Power State (ULPS) mode. + + qcom,suspend-ulps-enabled: + description: Boolean to enable support for ULPS mode for panels during suspend state. + + qcom,spr-pack-type: + description: > + String to specify the SPR pack type of panel pixel layout + Expected string for the pack types supported by MDSS are, + "pentile", "rgbw", "yygm", "yygw" + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,panel-roi-alignment: + description: | + Specifies the panel ROI alignment restrictions on its + left, top, width, height alignments and minimum width and + height values. This property is specified per timing node to support + resolution's alignment restrictions. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,esd-check-enabled: + description: Boolean used to enable ESD recovery feature. + + qcom,mdss-dsi-panel-status-command: + description: > + A byte stream formed by multiple dcs packets based on + qcom dsi controller protocol, to read the panel status. + This value is used to kick in the ESD recovery. + byte 0: dcs data type + byte 1: Unused + byte 2: virtual channel number + byte 3: expect ack from client (dcs read command) + byte 4: wait number of specified ms after dcs command + transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload + + qcom,mdss-dsi-panel-status-command-mode: + description: > + String that specifies the ctrl state for reading the panel status. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-lp1-command: + description: > + An optional byte stream to request low + power mode on a panel + + qcom,mdss-dsi-lp1-command-mode: + description: > + String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-lp2-command: + description: > + An optional byte stream to request ultra + low power mode on a panel + + qcom,mdss-dsi-lp2-command-mode: + description: > + String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-nolp-command: + description: An optional byte stream to disable low power and ultra low power panel modes + + qcom,mdss-dsi-nolp-command-mode: + description: > + String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-panel-status-check-mode: + description: > + Specifies the panel status check method for ESD recovery. + "bta_check" = Uses BTA to check the panel status + "reg_read" = Reads panel status register to check the panel status + "reg_read_nt35596" = Reads panel status register to check the panel + status for NT35596 panel. + "te_signal_check" = Uses TE signal behaviour to check the panel status + enum: [bta_check, reg_read, reg_read_nt35596, te_signal_check] + + qcom,mdss-dsi-panel-status-read-length: + description: > + Integer array that specify the expected read-back length of values + for each of panel registers. Each length is corresponding to number of + returned parameters of register introduced in specification. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,mdss-dsi-panel-status-valid-params: + description: > + Integer array that specify the valid returned values which need to check + for each of register. + Some panel need only check the first few values returned from panel. + So: if this property is the same to qcom,mdss-dsi-panel-status-read-length, + then just ignore this one. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,mdss-dsi-panel-status-value: + description: > + Multiple integer arrays, each specifies the values of the panel status register + which is used to check the panel status. The size of each array is the sum of + length specified in qcom,mdss-dsi-panel-status-read-length, and must be equal. + This can cover that Some panel may return several alternative values. + + qcom,mdss-dsi-panel-max-error-count: + description: > + Integer value that specifies the maximum number of errors from register + read that can be ignored before treating that the panel has gone bad. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dynamic-mode-switch-enabled: + description: > + Boolean used to mention whether panel supports + dynamic switching from video mode to command mode + and vice versa. + + qcom,dynamic-mode-switch-type: + description: > + A string specifies how to perform dynamic mode switch. + If qcom,dynamic-mode-switch-enabled is set and no string specified, default value is + dynamic-switch-suspend-resume. + "dynamic-switch-suspend-resume"= Switch using suspend/resume. Panel will + go blank during transition. + "dynamic-switch-immediate"= Switch on next frame update. Panel will + not go blank for this transition. + "dynamic-resolution-switch-immediate"= Switch the panel resolution. Panel will + not go blank for this transition. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-post-mode-switch-on-command: + description: > + Multiple dcs packets used for turning on DSI panel + after panel has switch modes. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,cmd-mode-switch-out-commands: + description: > + List of commands that need to be sent + to panel in order to switch out command mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,cmd-mode-switch-out-commands-state: + description: > + String that specifies the ctrl state for sending command mode switch out + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,cmd-mode-switch-in-commands: + description: > + List of commands that need to be sent + to panel in order to switch in command mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,cmd-mode-switch-in-commands-state: + description: > + String that specifies the ctrl state for sending command mode switch in + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,video-mode-switch-out-commands: + description: > + List of commands that need to be sent + to panel in order to switch out video mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,video-mode-switch-out-commands-state: + description: > + String that specifies the ctrl state for sending video mode switch out + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,video-mode-switch-in-commands: + description: > + List of commands that need to be sent + to panel in order to switch in video mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,video-mode-switch-in-commands-state: + description: > + String that specifies the ctrl state for sending video mode switch in + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,send-pps-before-switch: + description: > + Boolean propety to indicate when PPS commands should be sent, + either before or after switch commands during dynamic resolution + switch in DSC panels. If the property is not present, the default + behavior is to send PPS commands after the switch commands. + + qcom,mdss-dsi-panel-orientation: + description: > + String used to indicate orientation of panel + "180" = panel is flipped in both horizontal and vertical directions + "hflip" = panel is flipped in horizontal direction + "vflip" = panel is flipped in vertical direction + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,panel-ack-disabled: + description: > + A boolean property to indicate, whether we need to wait for any ACK from the panel + for any commands that we send. + + qcom,mdss-dsi-force-clock-lane-hs: + description: Boolean to force dsi clock lanes to HS mode always. + + qcom,panel-cphy-mode: + description: Boolean to specify whether panel is using cphy. + + qcom,compression-mode: + description: > + Select compression mode for panel. + "fbc" - frame buffer compression + "dsc" - display stream compression. + "vdc" - VESA display compression. + If "dsc" or "vdc" compression is used then config subnodes needs to be defined. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,panel-supply-entries: + description: > + A node that lists the elements of the supply used to + power the DSI panel. There can be more than one instance + of this binding, in which case the entry would be appended + with the supply entry index. For a detailed description of + fields in the supply entry, refer to the qcom,ctrl-supply-entries + binding above. + + qcom,mdss-dsc-version: + description: > + An 8 bit value indicates the DSC version supported by panel. Bits[0.3] + provides information about minor version while Bits[4.7] provides + major version information. It supports only DSC rev 1(Major).1(Minor) + right now. + + qcom,mdss-dsc-scr-version: + description: > + Each DSC version can have multiple SCR. This 8 bit value indicates + current SCR revision information supported by panel. + + qcom,mdss-dsc-encoders: + description: > + An integer value indicating how many DSC encoders should be used + to drive data stream to DSI. + Default value is 1 and max value is 2. + 2 encoder should be used only if qcom,mdss-lm-split or + qcom,split-mode with pingpong-split is used. + default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + + qcom,mdss-dsc-slice-height: + description: An integer value indicates the dsc slice height. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-slice-width: + description: > + An integer value indicates the dsc slice width. + Multiple of slice width should be equal to panel-width. + Maximum 2 slices per DSC encoder can be used so if 2 DSC encoders + are used then minimum slice width is equal to panel-width/4. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-slice-per-pkt: + description: An integer value indicates the slice per dsi packet. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-bit-per-component: + description: An integer value indicates the bits per component before compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-bit-per-pixel: + description: An integer value indicates the bits per pixel after compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-block-prediction-enable: + description: A boolean value to enable/disable the block prediction at decoder. + + qcom,mdss-dsc-config-by-manufacture-cmd: + description: > + A boolean to indicates panel use manufacture command to setup pps + instead of standard dcs type 0x0A. + + qcom,vdc-version: + description: > + An 8 bit value indicates the VDC version supported by panel. Bits[0.3] + provides information about minor version while Bits[4.7] provides + major version information. It supports only VDC rev 1(Major).2(Minor) + right now. + + qqcom,vdc-version-release: + description: An 8 bit value indicated VDC version release. This has to be set to 0. + const: 0 + + qcom,vdc-slice-height: + description: An u32 value which indicates slice height. This should be at least 16 lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-slice-width: + description: > + An u32 value which indicates slice width. This should be at least 64 pixels and + should also be a multiple of 8 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-slice-per-pkt: + description: An u32 value indicates the slice per dsi packet. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-bit-per-component: + description: An u32 value indicates the bits per component before compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-bit-per-pixel: + description: An u32 value indicates the bits per pixel after compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,src-color-space: + description: > + An u32 value indicating the source color space. It can either be RGB or YUV. + Default value is assumed to be RGB + 0 - RGB + 1 - YUV + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + enum: [0,1] + + qcom,src-chroma-format: + description: > + An u32 value indicating the source color space. It can either be 444, 420 or 422. + Default value is assumed to be 444 + 0 - 444 + 1 - 422 + 2 - 420 + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + enum: [0, 1, 2] + + qcom,mdss-pps-delay-ms: + description: > + An u32 value that indicates post PPS command + delay in milliseconds. If no value is specified, it chooses zero by default. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,display-topology: + description: > + Array of u32 values which specifies the list of topologies available + for the display. A display topology is defined by a + set of 3 values in the order: + - number of mixers + - number of compression encoders + - number of interfaces + Therefore, the array should always contain a tuple of 3 elements. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + - description: number of mixers + - description: number of compression encoders + - description: number of interfaces + + qcom,default-topology-index: + description: > + An u32 value which indexes the topology set + specified by the node "qcom,display-topology" + to identify the default topology for the + display. The first set is indexed by the + value 0. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-ext-bridge-mode: + description: External bridge chip is connected instead of panel. + + qcom,mdss-dsi-dma-schedule-line: + description: > + An integer value indicates the line number after vertical active + region for video mode panels and line number after TE for command mode + panels, at which command DMA needs to be triggered. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-dma-schedule-window: + description: > + An integer value indicates the width of the DMA window during which a + DCS command will be triggered for command mode panels + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-mdp-idle-ctrl-en: + description: > + A boolean to enable LP11 insertion after transmission of every line. + This requires command mdp burst mode to be disabled. + + qcom,mdss-dsi-mdp-idle-ctrl-len: + description: > + An u32 value indicating the number of dsi pclk cycles of idle time + to insert between command mode mdp packets. This time must be long + enough to cover the time link takes to switch between HS to LP11 mode. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vert-padding-value: + description: > + An u32 value indicating the second display height while using two displays + in shared display feature. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dba-panel: + description: > + Indicates whether the current panel is used as a display bridge + to a non-DSI interface. + + qcom,bridge-name: + description: > + A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name + is required if qcom,dba-panel is defined for the panel. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,adjust-timer-wakeup-ms: + description: > + An integer value to indicate the timer delay(in ms) to accommodate + s/w delay while configuring the event timer wakeup logic. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-display-timings: + description: > + Parent node that lists the different resolutions that the panel supports. + Each child represents timings settings for a specific resolution. + + qcom,mdss-dsi-post-init-delay: + description: > + Specifies required number of frames to wait so that panel can be functional + to show proper display. + + qcom,mdss-dsi-video-mode: + description: A boolean to indicates current timing can only work in video mode. + + qcom,mdss-dsi-cmd-mode: + description: A boolean to indicates current timing can only work in command mode. + +# Additional properties added to the second level nodes that represent timings properties: + + qcom,mdss-dsi-timing-default: + description: > + Property that specifies the current child as the default + timing configuration that will be used. + + qcom,mdss-dsi-timing-switch-command: + description: > + List of commands that need to be sent + to panel when the resolution/timing switch happens dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,mdss-dsi-timing-switch-command-state: + description: > + String that specifies the ctrl state for sending resolution switch + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,dsi-dyn-clk-list: + description: > + An u32 array of all the supported dsi bit clock + frequencies in Hz for the given mode, listed in + order of preference. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,disable-rsc-solver: + description: > + Timing node property to dynamically disable RSC solver for + high FPS usecase due to lower bitclk rate. + +required: + - compatible + - status + - qcom,mdss-dsi-panel-controller + - qcom,mdss-dsi-panel-width + - qcom,mdss-dsi-panel-height + - qcom,mdss-dsi-bpp + - qcom,mdss-dsi-panel-destination + - qcom,mdss-dsi-panel-timings + - qcom,mdss-dsi-panel-timings-8996 + - qcom,mdss-dsi-on-command + - qcom,mdss-dsi-off-command + - qcom,mdss-dsi-post-panel-on-command + - qcom,platform-reset-gpio + +if: + properties: + contains: + const: bl_ctrl_pwm +then: + required: + - qcom,mdss-dsi-bl-pmic-bank-select + - qcom,mdss-dsi-bl-pmic-pwm-frequency + - qcom,mdss-dsi-pwm-gpio + +examples: + - | + &mdss_mdp { + dsi_sim_vid: qcom,mdss_dsi_sim_video { + qcom,mdss-dsi-panel-name = "simulator video mode dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-pixel-packing = <0>; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-fbc-enable; + qcom,mdss-dsi-panel-mode-switch; + qcom,poms-align-panel-vsync; + qcom,mdss-dsi-bpp-switch; + qcom,mdss-dsi-fbc-slice-height = <5>; + qcom,mdss-dsi-fbc-2d-pred-mode; + qcom,mdss-dsi-fbc-ver2-mode; + qcom,mdss-dsi-fbc-bpp = <0>; + qcom,mdss-dsi-fbc-packing = <0>; + qcom,mdss-dsi-fbc-quant-error; + qcom,mdss-dsi-fbc-bias = <0>; + qcom,mdss-dsi-fbc-pat-mode; + qcom,mdss-dsi-fbc-vlc-mode; + qcom,mdss-dsi-fbc-bflc-mode; + qcom,mdss-dsi-fbc-h-line-budget = <0>; + qcom,mdss-dsi-fbc-budget-ctrl = <0>; + qcom,mdss-dsi-fbc-block-budget = <0>; + qcom,mdss-dsi-fbc-lossless-threshold = <0>; + qcom,mdss-dsi-fbc-lossy-threshold = <0>; + qcom,mdss-dsi-fbc-rgb-threshold = <0>; + qcom,mdss-dsi-fbc-lossy-mode-idx = <0>; + qcom,mdss-dsi-fbc-max-pred-err = <2>; + qcom,mdss-dsi-h-front-porch = <140>; + qcom,mdss-dsi-h-back-porch = <164>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <1>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = < 15>; + qcom,mdss-brightness-max-level = <255>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-interleave-mode = <0>; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <30>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-hfp-power-mode; + qcom,mdss-dsi-hbp-power-mode; + qcom,mdss-dsi-hsa-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-last-line-interleave; + qcom,mdss-dsi-traffic-mode = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-color-order = <0>; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x20>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-mdp-trigger = <0>; + qcom,mdss-dsi-dma-trigger = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 + 22 27 1e 03 04 00]; + qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 2e 06 08 05 03 04 a0]; + qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00 + 29 01 00 00 10 00 02 FF 99]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [22 01 00 00 00 00 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; + qcom,dsi-supported-dfps-list = <30 45 60>; + qcom,dsi-supported-qsync-min-fps-list = <30 40 55>; + qcom,dsi-qsync-avr-step-list = <0 360 660>; + qcom,dsi-qsync-avr-step-fps = <360>; + qcom,min-refresh-rate = <30>; + qcom,max-refresh-rate = <60>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>; + qcom,5v-boost-gpio = <&pm8994_gpios 14 0>; + qcom,mdss-pan-physical-width-dimension = <60>; + qcom,mdss-pan-physical-height-dimension = <140>; + qcom,mdss-dsi-mode-sel-gpio-state = "dsc_mode"; + qcom,mdss-tear-check-sync-cfg-height = <0xfff0>; + qcom,mdss-tear-check-sync-init-val = <1280>; + qcom,mdss-tear-check-sync-threshold-start = <4>; + qcom,mdss-tear-check-sync-threshold-continue = <4>; + qcom,mdss-tear-check-start-pos = <1280>; + qcom,mdss-tear-check-rd-ptr-trigger-intr = <1281>; + qcom,mdss-tear-check-frame-rate = <6000>; + qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-init-delay-us = <100>; + mdss-dsi-rx-eot-ignore; + mdss-dsi-tx-eot-append; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-read-length = <8>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-panel-status-value = <0x1c 0x00 0x05 0x02 0x40 0x84 0x06 0x01>; + qcom,dynamic-mode-switch-enabled; + qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; + qcom,mdss-dsi-post-mode-switch-on-command = [32 01 00 00 00 00 02 00 00 + 29 01 00 00 10 00 02 B0 03]; + qcom,video-to-cmd-mode-switch-commands = [15 01 00 00 00 00 02 C2 0B + 15 01 00 00 00 00 02 C2 08]; + qcom,cmd-to-video-mode-switch-commands = [15 01 00 00 00 00 02 C2 03]; + qcom,send-pps-before-switch; + qcom,panel-ack-disabled; + qcom,mdss-dsi-horizontal-line-idle = <0 40 256>, + <40 120 128>, + <128 240 64>; + qcom,mdss-dsi-panel-orientation = "180" + qcom,mdss-dsi-panel-jitter = <0x8 0x10>; + qcom,mdss-dsi-panel-prefill-lines = <0x10>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,compression-mode = "dsc"; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,platform-reset-gpio = <&tlmm 0 0>; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,mdss-dsi-display-timings { + wqhd { + cell-index = <0>; + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-bpp-mode = <24>; + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <728>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <424000000>; + qcom,mdss-mdp-transfer-time-us = <12500>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-mdp-transfer-time-us-min = <10000>; + qcom,mdss-mdp-transfer-time-us-max = <15000>; + qcom,mdss-dsi-panel-timings = [E6 38 26 00 68 6E 2A 3C 2C 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2a>; + qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 00 00 00 00 00 02 B0 04 + 29 00 00 00 00 00 02 F1 00]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; + qcom,qsync-mode-min-refresh-rate = <48>; + qcom,dsi-qsync-mode-avr-step-fps = <360>; + qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; + qcom,video-mode-switch-out-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 49]; + qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; + qcom,video-mode-switch-in-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 40]; + qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-in-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 42]; + qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-out-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 01 02 50]; + qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; + + qcom,dsi-dyn-clk-list = <524637388 525735938 528842882>; + + qcom,vert-padding-value = <2940>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsc-config-by-manufacture-cmd; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <4 4 2 2 20 20>; + }; + }; + qcom,panel-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <2800000>; + qcom,supply-max-voltage = <2800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + + qcom,dba-panel; + qcom,bridge-name = "adv7533"; + qcom,mdss-dsc-version = <0x11>; + qcom,mdss-dsc-scr-version = <0x1>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsc-config-by-manufacture-cmd; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <0>; + qcom,vdc-version = <0x12>; + qcom,vdc-version-release = <0>; + qcom,vdc-slice-height = <256>; + qcom,vdc-slice-width = <720>; + qcom,vdc-slice-per-pkt = <2>; + qcom,vdc-bit-per-component = <8>; + qcom,vdc-bit-per-pixel = <6>; + qcom,src-color-space = <0>; + qcom,src-chroma-format = <0>; + qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,mdss-dsi-dma-schedule-window = <50>; + }; + }; +... diff --git a/bindings/msm_hdcp.txt b/bindings/msm_hdcp.txt deleted file mode 100644 index 8d5f55d7..00000000 --- a/bindings/msm_hdcp.txt +++ /dev/null @@ -1,14 +0,0 @@ -MSM HDCP driver - -Standalone driver managing HDCP related communications -between TZ and HLOS for MSM chipset. - -Required properties: - -compatible = "qcom,msm-hdcp"; - -Example: - -qcom_msmhdcp: qcom,msm_hdcp { - compatible = "qcom,msm-hdcp"; -}; diff --git a/bindings/msm_hdcp.yaml b/bindings/msm_hdcp.yaml new file mode 100644 index 00000000..8ce3fccf --- /dev/null +++ b/bindings/msm_hdcp.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/msm_hdcp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSM HDCP driver + +description: | + Standalone driver managing HDCP related communications between TZ and HLOS for MSM chipset. + +maintainers: + - Rajkumar Subbiah + - Vishnuvardhan Prodduturi + +properties: + compatible: + const: qcom,msm-hdcp + +required: + - compatible + +examples: + - | + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; +... diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt deleted file mode 100644 index fb48ae98..00000000 --- a/bindings/sde-dp.txt +++ /dev/null @@ -1,297 +0,0 @@ -Qualcomm Technologies, Inc. -sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. -DP Controller: Required properties: -- compatible: Should be "qcom,dp-display". -- reg: Base address and length of DP hardware's memory mapped regions. -- reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. - "dp_ahb" - AHB memory region. - "dp_aux" - AUX memory region. - "dp_link" - LINK memory region. - "dp_p0" - PCLK0 memory region. - "dp_phy" - PHY memory region. - "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. - "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. - "dp_mmss_cc" - Display Clock Control memory region. - "dp_pll" - USB3 DP combo PLL memory region. - "usb3_dp_com" - USB3 DP PHY combo memory region. - "hdcp_physical" - DP HDCP memory region. - "dp_p1" - DP PCLK1 memory region. - "gdsc" - DISPCC GDSC memory region. -- cell-index: Specifies the controller instance. -- #clock-cells: Denotes the DP driver as a clock producer (has one or more clock outputs) -- clocks: Clocks required for Display Port operation. -- clock-names: Names of the clocks corresponding to handles. Following clocks are required: - "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", - "link_clk_src", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", - "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk". -- vdda-1p2-supply: phandle to vdda 1.2V regulator node. -- vdda-0p9-supply: phandle to vdda 0.9V regulator node. -- interrupt-parent phandle to the interrupt parent device node. -- interrupts: The interrupt signal from the DSI block. -- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg6-settings: Specifies the DP AUX configuration 6 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg7-settings: Specifies the DP AUX configuration 7 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg8-settings: Specifies the DP AUX configuration 8 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg9-settings: Specifies the DP AUX configuration 9 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port. -- qcom,mst-enable: MST feature enable control node. -- qcom,dsc-feature-enable: DSC feature enable control node. -- qcom,fec-feature-enable: FEC feature enable control node. -- qcom,qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask -- qcom,qos-cpu-latency-us: A u32 value indicating desired PM QoS CPU latency in usec -- qcom,altmode-dev: Phandle for the AltMode GLink driver. -- usb-controller: Phandle for the USB controller. -- qcom,pll-revision: PLL hardware revision. -- usb-phy: Phandle for USB PHY driver. This is used to register for USB cable events. -- qcom,dsc-continuous-pps: Control node for sending PPS every frame in hardware for DSC over DP. - This is needed by certain bridge chips where there is such a requirement to do so. -- qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. -- qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. -- qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. -- qcom,-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DP module. The module "types" - can be "core", "ctrl", "pll" and "phy". Within the same type, - there can be more than one instance of this binding, - in which case the entry would be appended with the - supply entry index. - e.g. qcom,ctrl-supply-entry@0 - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off - -msm_ext_disp is a device which manages the interaction between external -display interfaces, e.g. Display Port, and the audio subsystem. - -Optional properties: -- clock-mmrm: List of the clocks that enable setting the clk rate through MMRM driver. - The order of the list must match the 'clocks' and 'clock-names' - properties. The 'DISP_CC' ID of the clock must be used to enable - the property for the respective clock, whereas a value of zero - disables the property. -- vdd_mx-supply: phandle to vdda MX regulator node -- qcom,aux-en-gpio: Specifies the aux-channel enable gpio. -- qcom,aux-sel-gpio: Specifies the aux-channel select gpio. -- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio. -- qcom,ext-disp: phandle for msm-ext-display module -- compatible: Must be "qcom,msm-ext-disp" -- qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node -- qcom,phy-version: Phy version -- qcom,pn-swap-lane-map: P/N swap configuration of each lane -- pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node - Refer to pinctrl-bindings.txt -- pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin - controller. These pin configurations are installed in the pinctrl - device node. Refer to pinctrl-bindings.txt -- qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port. -- qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one -- qcom,hbr-rbr-voltage-swing: Specifies the voltage swing levels for HBR and RBR rates. -- qcom,hbr-rbr-pre-emphasis: Specifies the pre-emphasis levels for HBR and RBR rates. -- qcom,hbr2-3-voltage-swing: Specifies the voltage swing levels for HBR2 and HBR3 rates. -- qcom,hbr2-3-pre-emphasis: Specifies the pre-emphasis levels for HBR2 and HBR3 rates. - -[Optional child nodes]: These nodes are for devices which are -dependent on msm_ext_disp. If msm_ext_disp is disabled then -these devices will be disabled as well. Ex. Audio Codec device. - -- ext_disp_audio_codec: Node for Audio Codec. -- compatible : "qcom,msm-ext-disp-audio-codec-rx"; - -Example: - -ext_disp: qcom,msm-ext-disp { - compatible = "qcom,msm-ext-disp"; - - ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { - compatible = "qcom,msm-ext-disp-audio-codec-rx"; - }; -}; - -sde_dp: qcom,dp_display@0 { - cell-index = <0>; - compatible = "qcom,dp-display"; - - qcom,dp-aux-switch = <&fsa4480>; - qcom,ext-disp = <&ext_disp>; - qcom,altmode-dev = <&altmode 0>; - usb-controller = <&usb0>; - - reg = <0xae90000 0x0dc>, - <0xae90200 0x0c0>, - <0xae90400 0x508>, - <0xae91000 0x094>, - <0x88eaa00 0x200>, - <0x88ea200 0x200>, - <0x88ea600 0x200>, - <0xaf02000 0x1a0>, - <0x88ea000 0x200>, - <0x88e8000 0x20>, - <0x0aee1000 0x034>, - <0xae91400 0x094>, - <0xaf03000 0x8>; - reg-names = "dp_ahb", "dp_aux", "dp_link", - "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", - "dp_mmss_cc", "dp_pll", "usb3_dp_com", - "hdcp_physical", "dp_p1", "gdsc"; - - interrupt-parent = <&mdss_mdp>; - interrupts = <12 0>; - - #clock-cells = <1>; - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, - <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; - clock-names = "core_aux_clk", "core_usb_ref_clk_src", - "core_usb_pipe_clk", "link_clk", "link_clk_src", - "link_iface_clk", "pixel_clk_rcg", "pixel_parent", - "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; - clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>; - - qcom,pll-revision = "5nm-v1"; - qcom,phy-version = <0x420>; - qcom,dp-aux-switch = <&fsa4480>; - - qcom,aux-cfg0-settings = [1c 00]; - qcom,aux-cfg1-settings = [20 13 23 1d]; - qcom,aux-cfg2-settings = [24 00]; - qcom,aux-cfg3-settings = [28 00]; - qcom,aux-cfg4-settings = [2c 0a]; - qcom,aux-cfg5-settings = [30 26]; - qcom,aux-cfg6-settings = [34 0a]; - qcom,aux-cfg7-settings = [38 03]; - qcom,aux-cfg8-settings = [3c bb]; - qcom,aux-cfg9-settings = [40 03]; - qcom,max-pclk-frequency-khz = <593470>; - qcom,mst-enable; - qcom,dsc-feature-enable; - qcom,fec-feature-enable; - qcom,dsc-continuous-pps; - qcom,qos-cpu-mask = <0xf>; - qcom,qos-cpu-latency-us = <300>; - vdda-1p2-supply = <&L6B>; - vdda-0p9-supply = <&L1B>; - vdd_mx-supply = <&VDD_MXA_LEVEL>; - - qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, - <0x11 0x1e 0x1f 0xff>, - <0x16 0x1f 0xff 0xff>, - <0x1f 0xff 0xff 0xff>; - qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, - <0x00 0x0e 0x15 0xff>, - <0x00 0x0e 0xff 0xff>, - <0x02 0xff 0xff 0xff>; - - qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, - <0x09 0x19 0x1f 0xff>, - <0x10 0x1f 0xff 0xff>, - <0x1f 0xff 0xff 0xff>; - qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, - <0x02 0x0e 0x16 0xff>, - <0x02 0x11 0xff 0xff>, - <0x04 0xff 0xff 0xff>; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <21700>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <912000>; - qcom,supply-max-voltage = <912000>; - qcom,supply-enable-load = <115000>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,pll-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,pll-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd_mx"; - qcom,supply-min-voltage = - ; - qcom,supply-max-voltage = - ; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; -}; diff --git a/bindings/sde-dp.yaml b/bindings/sde-dp.yaml new file mode 100644 index 00000000..b8907930 --- /dev/null +++ b/bindings/sde-dp.yaml @@ -0,0 +1,579 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde-dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SDE DP + +description: | + sde-dp is the master Display Port device which supports DP host controllers that are compatible + with VESA Display Port interface specification. + msm_ext_disp is a device which manages the interaction between external + display interfaces, e.g. Display Port, and the audio subsystem. + [Optional child nodes]: These nodes are for devices which are + dependent on msm_ext_disp. If msm_ext_disp is disabled then + these devices will be disabled as well. Ex. Audio Codec device. + +maintainers: + - Rajkumar Subbiah + - Vishnuvardhan Prodduturi + +properties: + compatible: + const: qcom,dp-display + + reg: + description: | + Base address and length of DP hardware's memory mapped regions. + + reg-names: + description: | + A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. + "dp_ahb" - AHB memory region. + "dp_aux" - AUX memory region. + "dp_link" - LINK memory region. + "dp_p0" - PCLK0 memory region. + "dp_phy" - PHY memory region. + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. + "dp_mmss_cc" - Display Clock Control memory region. + "dp_pll" - USB3 DP combo PLL memory region. + "usb3_dp_com" - USB3 DP PHY combo memory region. + "hdcp_physical" - DP HDCP memory region. + "dp_p1" - DP PCLK1 memory region. + "gdsc" - DISPCC GDSC memory region. + + cell-index: + description: Specifies the controller instance. + + '#clock-cells': + description: Denotes the DP driver as a clock producer (has one or more clock outputs) + + clocks: + description: Clocks required for Display Port operation. + + clock-names: + items: + - const: core_aux_clk + - const: core_usb_ref_clk_src + - const: core_usb_pipe_clk + - const: link_clk + - const: link_clk_src + - const: link_iface_clk + - const: pixel_clk_rcg + - const: pixel_parent + - const: pixel1_clk_rcg + - const: strm0_pixel_clk + - const: strm1_pixel_clk + + vdda-1p2-supply: + description: phandle to vdda 1.2V regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + vdda-0p9-supply: + description: phandle to vdda 0.9V regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupt-parent: + description: phandle to the interrupt parent device node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + description: The interrupt signal from the DSI block. + + qcom,aux-cfg0-settings: + description: | + Specifies the DP AUX configuration 0 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg1-settings: + description: | + Specifies the DP AUX configuration 1 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg2-settings: + description: | + Specifies the DP AUX configuration 2 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg3-settings: + description: | + Specifies the DP AUX configuration 3 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg4-settings: + description: | + Specifies the DP AUX configuration 4 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg5-settings: + description: | + Specifies the DP AUX configuration 5 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg6-settings: + description: | + Specifies the DP AUX configuration 6 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg7-settings: + description: | + Specifies the DP AUX configuration 7 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg8-settings: + description: | + Specifies the DP AUX configuration 8 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg9-settings: + description: | + Specifies the DP AUX configuration 9 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,max-pclk-frequency-khz: + description: An integer specifying the max. pixel clock in KHz supported by Display Port. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mst-enable: + description: MST feature enable control node. + + qcom,dsc-feature-enable: + description: DSC feature enable control node. + + qcom,fec-feature-enable: + description: FEC feature enable control node. + + qcom,qos-cpu-mask: + description: A u32 value indicating desired PM QoS CPU affine mask + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,qos-cpu-latency-us: + description: A u32 value indicating desired PM QoS CPU latency in usec + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,altmode-dev: + description: Phandle for the AltMode GLink driver. + $ref: /schemas/types.yaml#/definitions/phandle + + usb-controller: + description: Phandle for the USB controller. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,pll-revision: + description: PLL hardware revision. + + usb-phy: + description: Phandle for USB PHY driver. This is used to register for USB cable events. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,dsc-continuous-pps: + description: | + Control node for sending PPS every frame in hardware for DSC over DP. + This is needed by certain bridge chips where there is such a requirement to do so. + + qcom,dp-aux-switch: + description: Phandle for the driver used to program the AUX switch for Display Port orientation. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,dp-hpd-gpio: + description: HPD gpio for direct DP connector without USB PHY or AUX switch. + + qcom,dp-gpio-aux-switch: + description: Gpio DP AUX switch chipset support. + + clock-mmrm: + description: | + List of the clocks that enable setting the clk rate through MMRM driver. + The order of the list must match the 'clocks' and 'clock-names' + properties. The 'DISP_CC' ID of the clock must be used to enable + the property for the respective clock, whereas a value of zero + disables the property. + + vdd_mx-supply: + description: phandle to vdda MX regulator node + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,aux-en-gpio: + description: Specifies the aux-channel enable gpio. + + qcom,aux-sel-gpio: + description: Specifies the aux-channel select gpio. + + qcom,usbplug-cc-gpio: + description: Specifies the usbplug orientation gpio. + + qcom,ext-disp: + description: phandle for msm-ext-display module + $ref: /schemas/types.yaml#/definitions/phandle + + compatible: + const: qcom,msm-ext-disp + + qcom,dp-low-power-hw-hpd: + description: Low power hardware HPD feature enable control node + + qcom,phy-version: + description: Phy version + + pinctrl-names: + description: | + List of names to assign mdss pin states defined in pinctrl device node + Refer to pinctrl-bindings.txt + + pinctrl-<0..n>: + description: | + Lists phandles each pointing to the pin configuration node within a pin + controller. These pin configurations are installed in the pinctrl + device node. Refer to pinctrl-bindings.txt + + qcom,max-lclk-frequency-khz: + description: An integer specifying the max. link clock in KHz supported by Display Port. + + qcom,mst-fixed-topology-ports: + description: u32 values of which MST output port to reserve, start from one + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hbr-rbr-voltage-swing: + description: Specifies the voltage swing levels for HBR and RBR rates. + + qcom,hbr-rbr-pre-emphasis: + description: Specifies the pre-emphasis levels for HBR and RBR rates. + + qcom,hbr2-3-voltage-swing: + description: Specifies the voltage swing levels for HBR2 and HBR3 rates. + + qcom,hbr2-3-pre-emphasis: + description: Specifies the pre-emphasis levels for HBR2 and HBR3 rates. + + compatible: + const: qcom,msm-ext-disp-audio-codec-rx + + ext_disp_audio_codec: + description: Node for Audio Codec. + +pattern properties: + "qcom,+\w+\-supply\-entries": + description: | + A node that lists the elements of the supply used by the + a particular "type" of DSI module. The module "types" + can be "core", "ctrl", and "phy". Within the same type, + there can be more than one instance of this binding, + in which case the entry would be appended with the + supply entry index. + e.g. qcom,ctrl-supply-entry@0 + type: object + patternProperties: + "qcom,ctrl\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,core\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,phy\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - reg-names + - cell-index + - '#clock-cells' + - clocks + - clock-names + - vdda-1p2-supply + - vdda-0p9-supply + - interrupt-parent + - interrupts + - qcom,aux-cfg0-settings + - qcom,aux-cfg1-settings + - qcom,aux-cfg2-settings + - qcom,aux-cfg3-settings + - qcom,aux-cfg4-settings + - qcom,aux-cfg5-settings + - qcom,aux-cfg6-settings + - qcom,aux-cfg7-settings + - qcom,aux-cfg8-settings + - qcom,aux-cfg9-settings + - qcom,max-pclk-frequency-khz + - qcom,mst-enable + - qcom,dsc-feature-enable + - qcom,fec-feature-enable + - qcom,qos-cpu-mask + - qcom,qos-cpu-latency-us + - qcom,altmode-dev + - usb-controller + - qcom,pll-revision + - usb-phy + - qcom,dp-aux-switch + - qcom,dp-hpd-gpio + - qcom,dp-gpio-aux-switch + - qcom,-supply-entries + +examples: + - | + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + - | + sde_dp: qcom,dp_display@0 { + cell-index = <0>; + compatible = "qcom,dp-display"; + + qcom,dp-aux-switch = <&fsa4480>; + qcom,ext-disp = <&ext_disp>; + qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02000 0x1a0>, + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x094>, + <0xaf03000 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical", "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>; + + qcom,pll-revision = "5nm-v1"; + qcom,phy-version = <0x420>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,aux-cfg0-settings = [1c 00]; + qcom,aux-cfg1-settings = [20 13 23 1d]; + qcom,aux-cfg2-settings = [24 00]; + qcom,aux-cfg3-settings = [28 00]; + qcom,aux-cfg4-settings = [2c 0a]; + qcom,aux-cfg5-settings = [30 26]; + qcom,aux-cfg6-settings = [34 0a]; + qcom,aux-cfg7-settings = [38 03]; + qcom,aux-cfg8-settings = [3c bb]; + qcom,aux-cfg9-settings = [40 03]; + qcom,max-pclk-frequency-khz = <593470>; + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + + qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, + <0x11 0x1e 0x1f 0xff>, + <0x16 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, + <0x00 0x0e 0x15 0xff>, + <0x00 0x0e 0xff 0xff>, + <0x02 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, + <0x09 0x19 0x1f 0xff>, + <0x10 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, + <0x02 0x0e 0x16 0xff>, + <0x02 0x11 0xff 0xff>, + <0x04 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +... diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt deleted file mode 100644 index db92a23d..00000000 --- a/bindings/sde-dsi.txt +++ /dev/null @@ -1,130 +0,0 @@ -Qualcomm Technologies, Inc. - -mdss-dsi is the master DSI device which supports multiple DSI host controllers -that are compatible with MIPI display serial interface specification. - -DSI Controller and PHY: -Required properties: -- compatible: Should be "qcom,dsi-ctrl-hw-v". Supported - versions include 2.4, 2.5, and 2.6. - eg: qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3, - qcom,dsi-ctrl-hw-v2.4, qcom,dsi-ctrl-hw-v2.5, - qcom,dsi-ctrl-hw-v2.6 - And for dsi phy driver: - qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, - qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2 -- reg: List of base address and length of memory mapped - regions of DSI controller, disp_cc and mdp_intf. -- reg-names: A list of strings that name the list of regs. - "dsi_ctrl" - DSI controller memory region. - "disp_cc_base" - Base address of disp_cc memory region. - "mdp_intf_base" - Base address of mdp_intf memory region. -- cell-index: Specifies the controller instance. -- clocks: Clocks required for DSI controller operation. -- clock-names: Names of the clocks corresponding to handles. Following - clocks are required: - "mdp_core_clk" - "iface_clk" - "core_mmss_clk" - "bus_clk" - "byte_clk" - "pixel_clk" - "core_clk" - "byte_clk_rcg" - "pixel_clk_rcg" -- pll-label Supported versions of DSI PLL: - dsi_pll_5nm -- gdsc-supply: phandle to gdsc regulator node. -- vdda-supply: phandle to vdda regulator node. -- vcca-supply: phandle to vcca regulator node. -- interrupt-parent phandle to the interrupt parent device node. -- interrupts: The interrupt signal from the DSI block. -- qcom,dsi-default-panel: Specifies the default panel. -- qcom,mdp: Specifies the mdp node which can find panel node from this. -- qcom,demura-panel-id: Specifies the u64 demura panel ID as an array <2> - If demura is not used this node must be set to <0,0>. - -Bus Scaling Data: -- qcom,msm-bus,name: String property describing MDSS client. -- qcom,msm-bus,num-cases: This is the number of bus scaling use cases - defined in the vectors property. This must be - set to <2> for MDSS DSI driver where use-case 0 - is used to remove BW votes from the system. Use - case 1 is used to generate bandwidth requestes - when sending command packets. -- qcom,msm-bus,num-paths: This represents number of paths in each bus - scaling usecase. This value depends on number of - AXI master ports dedicated to MDSS for - particular chipset. -- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, with a format - of (src, dst, ab, ib) which is defined at - Documentation/devicetree/bindings/arm/msm/msm_bus.txt. - DSI driver should always set average bandwidth - (ab) to 0 and always use instantaneous - bandwidth(ib) values. - -Optional properties: -- label: String to describe controller. -- qcom,platform-te-gpio: Specifies the gpio used for TE. -- qcom,panel-te-source: Specifies the source pin for Vsync from panel or WD Timer. -- qcom,dsi-ctrl: handle to dsi controller device -- qcom,dsi-phy: handle to dsi phy device -- qcom,dsi-ctrl-num: Specifies the DSI controllers to use for primary panel -- qcom,dsi-sec-ctrl-num: Specifies the DSI controllers to use for secondary panel -- qcom,dsi-phy-num: Specifies the DSI PHYs to use for primary panel -- qcom,dsi-sec-phy-num: Specifies the DSI PHYs to use for secondary panel -- qcom,dsi-select-clocks: Specifies the required clocks to use for primary panel -- qcom,dsi-select-sec-clocks: Specifies the required clocks to use for secondary panel -- qcom,dsi-display-list: Specifies the list of supported displays. -- qcom,dsi-manager: Specifies dsi manager is present -- qcom,dsi-display: Specifies dsi display is present -- qcom,hdmi-display: Specifies hdmi is present -- qcom,dp-display: Specified dp is present -- qcom,-supply-entries: A node that lists the elements of the supply used by the - a particular "type" of DSI module. The module "types" - can be "core", "ctrl", and "phy". Within the same type, - there can be more than one instance of this binding, - in which case the entry would be appended with the - supply entry index. - e.g. qcom,ctrl-supply-entry@0 - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split enabled, this time should not be higher - than two times the dsi link rate time. - If the property is not specified, then the default value is 14000 us. -- qcom,dsi-phy-pll-bypass: A boolean property that enables bypassing hardware access in DSI - PHY/PLL drivers to allow the DSI driver to run on emulation platforms - that might be missing those modules. -- - qcom,null-insertion-enabled: A boolean to enable NULL packet insertion feature for DSI controller. -- ports: This video port is used when external bridge is present. - The connection is modeled using the OF graph bindings - specified in Documentation/devicetree/bindings/graph.txt. - Video port 0 reg 0 is for the bridge output. The remote - endpoint phandle should be mipi_dsi_device device node. -- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. -- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" - or "center-spread". Default is "down-spread" if it is not specified. -- qcom,ssc-frequency-hz: Integer property to specify the spread frequency - to be programmed for the SSC. -- qcom,ssc-ppm: Integer property to specify the Parts per Million - value of SSC. -- qcom,avdd-regulator-gpio: Specifies the gpio pin used for avdd - power supply regulator. diff --git a/bindings/sde-dsi.yaml b/bindings/sde-dsi.yaml new file mode 100644 index 00000000..6e85620c --- /dev/null +++ b/bindings/sde-dsi.yaml @@ -0,0 +1,360 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MDSS DSI + +description: | + mdss-dsi is the master DSI device which supports multiple DSI host controllers + that are compatible with MIPI display serial interface specification. + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +pattern properties: + "qcom,+\w+\-supply\-entries": + description: | + A node that lists the elements of the supply used by the + a particular "type" of DSI module. The module "types" + can be "core", "ctrl", and "phy". Within the same type, + there can be more than one instance of this binding, + in which case the entry would be appended with the + supply entry index. + e.g. qcom,ctrl-supply-entry@0 + type: object + patternProperties: + "qcom,ctrl\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,core\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,phy\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + +properties: + compatible: + enum: + - qcom,dsi-ctrl-hw-v2.4 + - qcom,dsi-ctrl-hw-v2.5 + - qcom,dsi-ctrl-hw-v2.6 + - qcom,dsi-ctrl-hw-v2.7 + - qcom,dsi-ctrl-hw-v2.8 + - qcom,dsi-ctrl-hw-v2.9 + - qcom,dsi-phy-v3.0 + - qcom,dsi-phy-v4.0 + - qcom,dsi-phy-v4.1 + - qcom,dsi-phy-v4.2 + - qcom,dsi-phy-v4.3 + - qcom,dsi-phy-v4.3.2 + - qcom,dsi-phy-v5.2 + - qcom,dsi-phy-v7.2 + + reg: + description: | + List of base address and length of memory mapped + regions of DSI controller, disp_cc and mdp_intf. + + reg-names: + items: + - const: dsi_ctrl + - const: disp_cc_base + - const: mdp_intf_base + + cell-index: + description: Specifies the controller instance. + + clocks: + items: + - const: mdp_core_clk + - const: iface_clk + - const: core_mmss_clk + - const: bus_clk + - const: byte_clk + - const: pixel_clk + - const: core_clk + - const: byte_clk_rcg + - const: pixel_clk_rcg + + pll-label: + description: Supported versions of DSI PLL. + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_pll_5nm, dsi_pll_4nm, dsi_pll_3nm] + + gdsc-supply: + description: phandle to gdsc regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + vdda-supply: + description: phandle to vdda regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + vcca-supply: + description: phandle to vcca regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupt-parent: + description: phandle to the interrupt parent device node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + description: The interrupt signal from the DSI block. + + qcom,dsi-default-panel: + description: Specifies the default panel. + + qcom,mdp: + description: Specifies the mdp node which can find panel node from this. + + qcom,demura-panel-id: + description: | + Specifies the u64 demura panel ID as an array <2> + If demura is not used this node must be set to <0,0>. + $ref: /schemas/types.yaml#/definitions/uint64 + + qcom,msm-bus,name: + description: String property describing MDSS client. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,msm-bus,num-cases: + description: | + This is the number of bus scaling use cases + defined in the vectors property. This must be + set to <2> for MDSS DSI driver where use-case 0 + is used to remove BW votes from the system. Use + case 1 is used to generate bandwidth requestes + when sending command packets. + + qcom,msm-bus,num-paths: + description: | + This represents number of paths in each bus + scaling usecase. This value depends on number of + AXI master ports dedicated to MDSS for + particular chipset. + + qcom,msm-bus,vectors-KBps: + description: | + A series of 4 cell properties, with a format + of (src, dst, ab, ib) which is defined at + Documentation/devicetree/bindings/arm/msm/msm_bus.txt. + DSI driver should always set average bandwidth + (ab) to 0 and always use instantaneous + bandwidth(ib) values. + + label: + description: String to describe controller. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,platform-te-gpio: + description: Specifies the gpio used for TE. + + qcom,panel-te-source: + description: Specifies the source pin for Vsync from panel or WD Timer. + + qcom,dsi-ctrl: + description: handle to dsi controller device + + qcom,dsi-phy: + description: handle to dsi phy device + + qcom,dsi-ctrl-num: + description: Specifies the DSI controllers to use for primary panel + + qcom,dsi-sec-ctrl-num: + description: Specifies the DSI controllers to use for secondary panel + + qcom,dsi-phy-num: + description: Specifies the DSI PHYs to use for primary panel + + qcom,dsi-sec-phy-num: + description: Specifies the DSI PHYs to use for secondary panel + + qcom,dsi-select-clocks: + description: Specifies the required clocks to use for primary panel + + qcom,dsi-select-sec-clocks: + description: Specifies the required clocks to use for secondary panel + + qcom,dsi-display-list: + description: Specifies the list of supported displays. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,dsi-manager: + description: Specifies dsi manager is present + + qcom,dsi-display: + description: Specifies dsi display is present + + qcom,hdmi-display: + description: Specifies hdmi is present + + qcom,dp-display: + description: Specified dp is present + + qcom,mdss-mdp-transfer-time-us: + description: | + Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. + + qcom,dsi-phy-pll-bypass: + description: | + A boolean property that enables bypassing hardware access in DSI + PHY/PLL drivers to allow the DSI driver to run on emulation platforms + that might be missing those modules. + + qcom,null-insertion-enabled: + description: A boolean to enable NULL packet insertion feature for DSI controller. + + ports: + description: | + This video port is used when external bridge is present. + The connection is modeled using the OF graph bindings + specified in Documentation/devicetree/bindings/graph.txt. + Video port 0 reg 0 is for the bridge output. The remote + endpoint phandle should be mipi_dsi_device device node. + + qcom,dsi-pll-ssc-en: + description: Boolean property to indicate that ssc is enabled. + + qcom,dsi-pll-ssc-mode: + description: | + Spread-spectrum clocking. It can be either "down-spread" + or "center-spread". Default is "down-spread" if it is not specified. + $ref: /schemas/types.yaml#/definitions/string-array + default: down-spread + enum: [down-spread, center-spread] + + qcom,ssc-frequency-hz: + description: | + Integer property to specify the spread frequency + to be programmed for the SSC. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,ssc-ppm: + description: Integer property to specify the Parts per Million value of SSC. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,avdd-regulator-gpio: + description: Specifies the gpio pin used for avdd power supply regulator. + +required: + - compatible + - reg + - reg-names + - cell-index + - clocks + - clock-names + - pll-label + - gdsc-supply + - vdda-supply + - vcca-supply + - interrupt-parent + - qcom,dsi-default-panel + - qcom,mdp + - qcom,demura-panel-id + - qcom,msm-bus,name + - qcom,msm-bus,num-cases + - qcom,msm-bus,num-paths + - qcom,msm-bus,vectors-KBps + +... diff --git a/bindings/sde-wb.txt b/bindings/sde-wb.txt deleted file mode 100644 index 90093e41..00000000 --- a/bindings/sde-wb.txt +++ /dev/null @@ -1,23 +0,0 @@ -Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display - -Required properties: -- compatible: "qcom,wb-display" - -Optional properties: -- cell-index: Index of writeback device instance. - Default to 0 if not specified. -- label: String to describe this writeback display. - Default to "unknown" if not specified. - -Example: - -/ { - ... - - sde_wb: qcom,wb-display { - compatible = "qcom,wb-display"; - cell-index = <2>; - label = "wb_display"; - }; - -}; diff --git a/bindings/sde-wb.yaml b/bindings/sde-wb.yaml new file mode 100644 index 00000000..b87ecaf9 --- /dev/null +++ b/bindings/sde-wb.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde-wb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display + +maintainers: + - Veera Sundaram Sankaran + - Kalyan Thota + - Ravi Teja Tamatam + +properties: + compatible: + const: qcom,wb-display + + cell-index: + description: Index of writeback device instance. Default to 0 if not specified. + default: 0 + + label: + description: String to describe this writeback display. Default to "unknown" if not specified. + default: "unknown" + +required: + - compatible + +examples: + - | + sde_wb: qcom,wb-display { + compatible = "qcom,wb-display"; + cell-index = <2>; + label = "wb_display"; + }; +... diff --git a/bindings/sde.txt b/bindings/sde.txt deleted file mode 100644 index 485ca56d..00000000 --- a/bindings/sde.txt +++ /dev/null @@ -1,1147 +0,0 @@ -Qualcomm Technologies, Inc. SDE KMS - -Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user -interface to different panel interfaces. SDE driver is the core of -display subsystem which manage all data paths to different panel interfaces. - -Required properties -- compatible: Must be "qcom,sde-kms" -- compatible: "msm-hdmi-audio-codec-rx"; -- reg: Offset and length of the register set for the device. -- reg-names : Names to refer to register sets related to this device -- clocks: List of Phandles for clock device nodes - needed by the device. -- clock-names: List of clock names needed by the device. -- mmagic-supply: Phandle for mmagic mdss supply regulator device node. -- vdd-supply: Phandle for vdd regulator device node. -- interrupt-parent: Must be core interrupt controller. -- interrupts: Interrupt associated with MDSS. -- interrupt-controller: Mark the device node as an interrupt controller. -- #interrupt-cells: Should be one. The first cell is interrupt number. -- iommus: Specifies the SID's used by this context bank. -- qcom,sde-sspp-type: Array of strings for SDE source surface pipes type information. - A source pipe can be "vig", "rgb", "dma" or "cursor" type. - Number of xin ids defined should match the number of offsets - defined in property: qcom,sde-sspp-off. -- qcom,sde-sspp-off: Array of offset for SDE source surface pipes. The offsets - are calculated from register "mdp_phys" defined in - reg property + "sde-off". The number of offsets defined here should - reflect the amount of pipes that can be active in SDE for - this configuration. -- qcom,sde-sspp-xin-id: Array of VBIF clients ids (xins) corresponding - to the respective source pipes. Number of xin ids - defined should match the number of offsets - defined in property: qcom,sde-sspp-off. -- qcom,sde-ctl-off: Array of offset addresses for the available ctl - hw blocks within SDE, these offsets are - calculated from register "mdp_phys" defined in - reg property. The number of ctl offsets defined - here should reflect the number of control paths - that can be configured concurrently on SDE for - this configuration. -- qcom,sde-wb-off: Array of offset addresses for the programmable - writeback blocks within SDE. -- qcom,sde-wb-xin-id: Array of VBIF clients ids (xins) corresponding - to the respective writeback. Number of xin ids - defined should match the number of offsets - defined in property: qcom,sde-wb-off. -- qcom,sde-mixer-off: Array of offset addresses for the available - mixer blocks that can drive data to panel - interfaces. These offsets are be calculated from - register "mdp_phys" defined in reg property. - The number of offsets defined should reflect the - amount of mixers that can drive data to a panel - interface. -- qcom,sde-dspp-top-off: Offset address for the dspp top block. - The offset is calculated from register "mdp_phys" - defined in reg property. -- qcom,sde-dspp-off: Array of offset addresses for the available dspp - blocks. These offsets are calculated from - register "mdp_phys" defined in reg property. -- qcom,sde-pp-off: Array of offset addresses for the available - pingpong blocks. These offsets are calculated - from register "mdp_phys" defined in reg property. -- qcom,sde-pp-slave: Array of flags indicating whether each ping pong - block may be configured as a pp slave. -- qcom,sde-pp-merge-3d-id: Array of index ID values for the merge 3d block - connected to each pingpong, starting at 0. -- qcom,sde-merge-3d-off: Array of offset addresses for the available - merge 3d blocks. These offsets are calculated - from register "mdp_phys" defined in reg property. -- qcom,sde-intf-off: Array of offset addresses for the available SDE - interface blocks that can drive data to a - panel controller. The offsets are calculated - from "mdp_phys" defined in reg property. The number - of offsets defined should reflect the number of - programmable interface blocks available in hardware. -- qcom,sde-mixer-blend-op-off Array of offset addresses for the available - blending stages. The offsets are relative to - qcom,sde-mixer-off. -- qcom,sde-mixer-pair-mask Array of mixer numbers that can be paired with - mixer number corresponding to the array index. - -Optional properties: -- clock-rate: List of clock rates in Hz. -- clock-max-rate: List of maximum clock rate in Hz that this device supports. -- clock-mmrm: List of clocks that enable setting the clk rate through MMRM driver. - The order of the list must match the 'clocks' and 'clock-names' properties. - The 'DISP_CC' ID of the clock must be used to enable the property for the - respective clock, whereas a value of zero disables the property. -- qcom,platform-supply-entries: A node that lists the elements of the supply. There - can be more than one instance of this binding, - in which case the entry would be appended with - the supply entry index. - e.g. qcom,platform-supply-entry@0 - -- reg: offset and length of the register set for the device. - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off -- qcom,sde-hw-version: A u32 value indicates the MDSS hw version -- qcom,hw-fence-sw-version: A u32 value to indicate the hw fencing version. If set to a value - greather than zero, driver will attempt to enable the feature (if - supported by the HW). Otherwise, if this value is not set or set - to zero, feature will remain disabled. -- qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp. -- qcom,sde-mixer-size: A u32 value indicates the address range for each mixer. -- qcom,sde-ctl-size: A u32 value indicates the address range for each ctl. -- qcom,sde-dspp-size: A u32 value indicates the address range for each dspp. -- qcom,sde-intf-size: A u32 value indicates the address range for each intf. -- qcom,sde-dsc-size: A u32 value indicates the address range for each dsc. -- qcom,sde-vdc-size: A u32 value indicates the address range for each vdc. -- qcom,sde-cdm-size: A u32 value indicates the address range for each cdm. -- qcom,sde-pp-size: A u32 value indicates the address range for each pingpong. -- qcom,sde-merge-3d-size: A u32 value indicates the address range for each merge 3d. -- qcom,sde-pp-cwb: Array of u32 flags indicating whether each ping pong - block may be configured as a cwb pp block. -- qcom,sde-wb-size: A u32 value indicates the address range for each writeback. -- qcom,sde-len: A u32 entry for SDE address range. -- qcom,sde-intf-max-prefetch-lines: Array of u32 values for max prefetch lines on - each interface. -- qcom,sde-sspp-linewidth: A u32 value indicates the max sspp line width. -- qcom,sde-vig-sspp-linewidth: A u32 value indicates the max vig sspp line width. -- qcom,sde-scaling-linewidth: A u32 value indicates the max vig source pipe line width - for scaling purposes. -- qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width. -- qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width. -- qcom,sde-wb-linewidth-linear: A u32 value indicates the max line width - supported by WB for linear color formats. -- qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. -- qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for - alpha blending. -- qcom,sde-qseed-sw-lib-rev: A string entry indicates qseed sw library revision - supporting the qseed HW block. It supports - "qseedv3", "qseedv3lite" and "qseedv2" entries for qseed - revision. By default "qseedv2" is used if this - optional property is not defined. -- qcom,sde-qseed-scalar-version: A u32 value indicating the HW version of the - QSEED hardware block -- qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. - It supports "csc" and "csc-10bit" entries for csc - type. -- qcom,sde-highest-bank-bit: Property to specify GPU/Camera/Video highest memory - bank bit used for tile format buffers. First value - in the array represents the ddr type and the second - value is the hbb value corresponding to the ddr type. -- qcom,sde-ubwc-version: Property to specify the UBWC feature version. A u32 UBWC version is based on MDSS support. -- qcom,sde-ubwc-static: Property to specify the default UBWC static - configuration value. -- qcom,sde-ubwc-bw-calc-version: A u32 property to specify version of UBWC bandwidth - calculation algorithm -- qcom,sde-ubwc-swizzle: Property to specify the default UBWC swizzle - configuration value. -- qcom,sde-smart-panel-align-mode: A u32 property to specify the align mode for - split display on smart panel. Possible values: - 0x0 - no alignment - 0xc - align at start of frame - 0xd - align at start of line -- qcom,sde-panic-per-pipe: Boolean property to indicate if panic signal - control feature is available on each source pipe. -- qcom,sde-has-src-split: Boolean property to indicate if source split - feature is available or not. -- qcom,sde-has-dim-layer: Boolean property to indicate if mixer has dim layer - feature is available or not. -- qcom,sde-has-idle-pc: Boolean property to indicate if target has idle - power collapse feature available or not. -- qcom,sde-wakeup-with-touch: Boolean property to indicate if command mode display - will exit from power collapse based on display input - touch event or not. -- qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction - feature available or not. -- qcom,sde-has-dest-scaler: Boolean property to indicate if destination scaler - feature is available or not. -- qcom,sde-max-dest-scaler-input-linewidth: A u32 value indicates the - maximum input line width to destination scaler. -- qcom,sde-max-dest-scaler-output-linewidth: A u32 value indicates the - maximum output line width of destination scaler. -- qcom,sde-dest-scaler-top-off: A u32 value provides the - offset from mdp base to destination scaler block. -- qcom,sde-dest-scaler-top-size: A u32 value indicates the address range for ds top -- qcom,sde-dest-scaler-off: Array of u32 offsets indicate the qseed3 scaler blocks - offset from destination scaler top offset. -- qcom,sde-dest-scaler-size: A u32 value indicates the address range for each scaler block -- qcom,sde-sspp-clk-ctrl: Array of offsets describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-sspp-off -- qcom,sde-sspp-clk-status: Array of offsets describing clk status - offsets for clock active state. 1st value - in the array represents offset of the status - register. 2nd value represents bit offset within - status register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-sspp-off. -- qcom,sde-sspp-excl-rect: Array of u32 values indicating exclusion rectangle - support on each sspp. -- qcom,sde-sspp-smart-dma-priority: Array of u32 values indicating hw pipe - priority of secondary rectangles when smart dma - is supported. Number of priority values should - match the number of offsets defined in - qcom,sde-sspp-off node. Zero indicates no support - for smart dma for the sspp. -- qcom,sde-smart-dma-rev: A string entry indicating the smart dma version - supported on the device. Supported entries are - "smart_dma_v1" and "smart_dma_v2". -- qcom,sde-vdc-hw-rev: A string indicating the hw version of vdc. -- qcom,sde-intf-type: Array of string provides the interface type information. - Possible string values - "dsi" - dsi display interface - "dp" - Display Port interface - "hdmi" - HDMI display interface - An interface is considered as "none" if interface type - is not defined. -- qcom,sde-intf-tear-irq-off Array of offset addresses for the available - tear effect (TE) IRQ blocks from "mdp_phys". - There should be one entry per INTF instance with - a zero value for INTFs without TE IRQ block. -- qcom,sde-emulated-env: Boolean property to indicate if the MDSS is running in an - emulated environment. -- qcom,sde-off: SDE offset from "mdp_phys" defined in reg property. -- qcom,sde-cdm-off: Array of offset addresses for the available - cdm blocks. These offsets will be calculated from - register "mdp_phys" defined in reg property. -- qcom,sde-vbif-off: Array of offset addresses for the available - vbif blocks. These offsets will be calculated from - register "vbif_phys" defined in reg property. -- qcom,sde-vbif-size: A u32 value indicates the vbif block address range. -- qcom,sde-uidle-off: A u32 value with the offset for the uidle - block, from the "mdp_phys". -- qcom,sde-uidle-size: A u32 value indicates the uidle block address range. -- qcom,sde-te-off: A u32 offset indicates the te block offset on pingpong. - This offset is 0x0 by default. -- qcom,sde-te2-off: A u32 offset indicates the te2 block offset on pingpong. -- qcom,sde-te-size: A u32 value indicates the te block address range. -- qcom,sde-te2-size: A u32 value indicates the te2 block address range. -- qcom,sde-dsc-off: Array of offset addresses for the available dsc - blocks. These offsets are calculated from - register "mdp_phys" defined in reg property. -- qcom,sde-dsc-hw-rev: A string value indicates the dsc hw block - version. -- qcom,sde-dsc-enc: Array of offset addresses for the available dsc - encoder blocks. These offsets are calculated from - the corresponding DSC base. -- qcom,sde-dsc-enc-size A u32 value indicates the enc block offset range. -- qcom,sde-dsc-ctl: Array of offset addresses for the available dsc - ctl blocks. These offsets are calculated from - the corresponding DSC base. -- qcom,sde-dsc-ctl-size A u32 value indicates the ctl block offset range. -- qcom,sde-dsc-native422-supp: Array of flags indicating whether corresponding dsc - block can support native 422 and native 420 - encoding. -- qcom,sde-dsc-linewidth: A u32 value indicates the max dsc line width. -- qcom,sde-vdc-off: A u32 offset address for the available vdc blocks. - This offset is calculated from register "mdp_phys" - defined in reg property. -- qcom,sde-vdc-enc-size A u32 value indicates the enc block offset range. -- qcom,sde-vdc-enc: A u32 offset address for the vdc encoder block. This offset is - calculated from qcom,sde-vdc-off. -- qcom,sde-vdc-ctl: A u32 offset address for the vdc ctl block. This offset is - calculated from qcom,sde-vdc-off. -- qcom,sde-vdc-ctl-size A u32 value indicates the ctl block offset range. -- qcom,sde-qdss-off: A u32 offset indicates the qdss block offset. -- qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong. -- qcom,sde-dither-version: A u32 value indicates the dither block version. -- qcom,sde-dither-size: A u32 value indicates the dither block address range. -- qcom,sde-cwb-dither: Array of u32 flags indicating whether each dither block - may be configured as a cwb dither block. -- qcom,sde-sspp-vig-blocks: A node that lists the blocks inside the VIG hardware. There can - be more than one instance of this binding, in which case the - entry would be appended with the vcm entry index. Each entry will - contain the offset and version (if needed) of each feature block. - The presence of a block entry indicates that the SSPP VIG contains - that feature hardware. - e.g. qcom,sde-sspp-vig-blocks - -- vcm@0 - -- cell-index: A u32 index for the sub-block. - -- qcom,sde-vig-top-off: A u32 offset of the sub-block top. - -- qcom,sde-vig-csc-off: offset of CSC hardware - -- qcom,sde-vig-qseed-off: offset of QSEED hardware - -- qcom,sde-vig-qseed-size: A u32 address range for qseed scaler. - -- qcom,sde-vig-pcc: offset and version of PCC hardware - -- qcom,sde-vig-hsic: offset and version of global PA adjustment - -- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware - -- qcom,sde-vig-gamut: offset and version of 3D LUT Gamut hardware - -- qcom,sde-vig-igc: offset and version of 1D LUT IGC hardware - -- qcom,sde-vig-inverse-pma: Boolean property to indicate if - inverse PMA feature is available on VIG pipe - -- qcom,sde-fp16-igc: u32 offset and version of the FP16 IGC hardware - -- qcom,sde-fp16-unmult: u32 offset and version of the FP16 Unmult hardware - -- qcom,sde-fp16-gc: u32 offset and version of the FP16 GC hardware - -- qcom,sde-fp16-csc: u32 offset and version of the FP16 CSC hardware - -- qcom,sde-ucsc-igc: u32 offset and version of the UCSC - IGC hardware - -- qcom,sde-ucsc-unmult: u32 offset and version of the UCSC - Unmult hardware - -- qcom,sde-ucsc-gc: u32 offset and version of the UCSC - GC hardware - -- qcom,sde-ucsc-csc: u32 offset and version of the UCSC - CSC hardware - -- qcom,sde-ucsc-alpha-dither: u32 offset and version of the UCSC - Alpha Dither hardware -- qcom,sde-sspp-dma-blocks: A node that lists the blocks inside the DMA hardware. There - can be more than one instance of this binding, in which case the - entry would be appended with dgm entry index. Each entry will - contain the offset and version (if needed) of each feature block. - The presence of a block entry indicates that the SSPP DMA contains - that feature hardware. - e.g. qcom,sde-sspp-dma-blocks - -- dgm@0 - -- cell-index: A u32 index for the sub-block. - -- qcom,sde-dma-top-off: A u32 offset of the sub-block top. - -- qcom,sde-dma-igc: offset and version of DMA IGC - -- qcom,sde-dma-gc: offset and version of DMA GC - -- qcom,sde-dma-inverse-pma: Boolean property to indicate if - inverse PMA feature is available on DMA pipe - -- qcom,sde-dma-csc-off: offset of CSC hardware - -- qcom,sde-fp16-igc: u32 offset and version of the FP16 IGC hardware - -- qcom,sde-fp16-unmult: u32 offset and version of the FP16 Unmult hardware - -- qcom,sde-fp16-gc: u32 offset and version of the FP16 GC hardware - -- qcom,sde-fp16-csc: u32 offset and version of the FP16 CSC hardware - -- qcom,sde-ucsc-igc: u32 offset and version of the UCSC - IGC hardware - -- qcom,sde-ucsc-unmult: u32 offset and version of the UCSC - Unmult hardware - -- qcom,sde-ucsc-gc: u32 offset and version of the UCSC - GC hardware - -- qcom,sde-ucsc-csc: u32 offset and version of the UCSC - CSC hardware - -- qcom,sde-ucsc-alpha-dither: u32 offset and version of the UCSC - Alpha Dither hardware -- qcom,sde-sspp-rgb-blocks: A node that lists the blocks inside the RGB hardware. The - block entries will contain the offset and version (if needed) - of each feature block. The presence of a block entry - indicates that the SSPP RGB contains that feature hardware. - e.g. qcom,sde-sspp-rgb-blocks - -- qcom,sde-rgb-scaler-off: offset of RGB scaler hardware - -- qcom,sde-rgb-scaler-size: A u32 address range for scaler. - -- qcom,sde-rgb-pcc: offset and version of PCC hardware -- qcom,sde-dspp-blocks: A node that lists the blocks inside the DSPP hardware. The - block entries will contain the offset and version of each - feature block. The presence of a block entry indicates that - the DSPP contains that feature hardware. - e.g. qcom,sde-dspp-blocks - -- qcom,sde-dspp-pcc: offset and version of PCC hardware - -- qcom,sde-dspp-gc: offset and version of GC hardware - -- qcom,sde-dspp-igc: offset and version of IGC hardware - -- qcom,sde-dspp-hsic: offset and version of global PA adjustment - -- qcom,sde-dspp-memcolor: offset and version of PA memcolor hardware - -- qcom,sde-dspp-sixzone: offset and version of PA sixzone hardware - -- qcom,sde-dspp-gamut: offset and version of Gamut mapping hardware - -- qcom,sde-dspp-dither: offset and version of dither hardware - -- qcom,sde-dspp-hist: offset and version of histogram hardware - -- qcom,sde-dspp-vlut: offset and version of PA vLUT hardware -- qcom,sde-mixer-blocks: A node that lists the blocks inside the layer mixer hardware. The - block entries will contain the offset and version (if needed) - of each feature block. The presence of a block entry - indicates that the layer mixer contains that feature hardware. - e.g. qcom,sde-mixer-blocks - -- qcom,sde-mixer-gc: offset and version of mixer GC hardware -- qcom,sde-dspp-ad-off: Array of u32 offsets indicate the ad block offset from the - DSPP offset. Since AD hardware is represented as part of - DSPP block, the AD offsets must be offset from the - corresponding DSPP base. -- qcom,sde-dspp-ad-version A u32 value indicating the version of the AD hardware -- qcom,sde-dspp-ltm-version A u32 value indicating the major(upper 16 bits) and minor(lower 16 bits) - version of the LTM hardware -- qcom,sde-dspp-ltm-off: Array of u32 offsets indicate the LTM block offsets from the - DSPP offsets. Since LTM hardware is represented as part of - DSPP block, the LTM offsets are calculated based on the - corresponding DSPP base. -- qcom,sde-dspp-rc-version: A u32 value indicating the version of the RC hardware. -- qcom,sde-dspp-rc-off: Array of u32 offsets indicate the RC block offsets from the - DSPP offsets. Since RC hardware is represented as part of - DSPP block, the RC offsets are calculated based on the - corresponding DSPP base. -- qcom,sde-dspp-rc-size: A u32 value indicating the RC block address range. -- qcom,sde-dspp-rc-mem-size: A u32 value indicating the RC block shared memory size. -- qcom,sde-dspp-rc-min-region-width: A u32 value indicating the RC block minimum region width. -- qcom,sde-dspp-spr-off: Array of u32 offsets indicate the SPR block offsets from the - corresponding DSPP block offset as base. -- qcom,sde-dspp-spr-size: A u32 value indicating the SPR block register address range -- qcom,sde-dspp-spr-version: A u32 value indicating the version of SPR hardware. -- qcom,sde-dspp-demura-off: Array of u32 offsets indicate the demura block offsets from the - corresponding DSPP block offset as base. -- qcom,sde-dspp-demura-size: A u32 value indicating the demura block register address range -- qcom,sde-dspp-demura-version: A u32 value indicating the version of demura hardware. -- qcom,sde-dspp-aiqe-off: Array of u32 values indicating the offset of each AIQE block - relative to its parent DSPP block. -- qcom,sde-dspp-aiqe-version: A u32 value indicating the version of the AIQE hardware. -- qcom,sde-dspp-aiqe-size: A u32 value indicating the shared memory size of each AIQE - hardware block instance. -- qcom,sde-dspp-aiqe-dither-off: Array of u32 values indicating the offset of each AIQE - dither block relative to its parent DSPP block. -- qcom,sde-dspp-aiqe-dither-version: A u32 value indicating the version of the AIQE dither - hardware. -- qcom,sde-dspp-aiqe-dither-size: A u32 value indicating the shared memory size of each AIQE - dither hardware block instance. -- qcom,sde-dspp-aiqe-wrapper-off: Array of u32 values indicating the offset of each AIQE - wrapper block relative to its parent DSPP block. -- qcom,sde-dspp-aiqe-wrapper-version: A u32 value indicating the version of the AIQE wrapper - hardware. -- qcom,sde-dspp-aiqe-wrapper-size: A u32 value indicating the shared memory size of each AIQE - wrapper hardware block instance. -- qcom,sde-dspp-aiqe-aiscaler-off: Array of u32 values indicating the offset of each AIQE - AI Scaler block relative to its parent DSPP block. -- qcom,sde-dspp-aiqe-aiscaler-version: A u32 value indicating the version of the AIQE AI Scaler - hardware. -- qcom,sde-dspp-aiqe-aiscaler-size: A u32 value indicating the shared memory size of each AIQE - AI Scaler hardware block instance. -- qcom,sde-aiqe-has-feature-mdnie: Boolean property indicating the presence of AIQE feature mDNIe - hardware. -- qcom,sde-aiqe-has-feature-abc: Boolean property indicating the presence of AIQE feature ABC - hardware. -- qcom,sde-aiqe-has-feature-ssrc: Boolean property indicating the presence of AIQE feature SSRC - hardware. -- qcom,sde-aiqe-has-feature-copr: Boolean property indicating the presence of AIQE feature COPR - hardware. -- qcom,sde-aiqe-has-feature-aiscaler: Boolean property indicating the presence of AIQE feature - AI Scaler hardware. -- nvmem-cells: phandle list to the fuse configuration data provided by a nvmem device. -- nvmem-cell-names: nvmem cell name. -- qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base. -- qcom,sde-lm-noise-version: A u32 value indicating the noise layer version. -- qcom,sde-vbif-id: Array of vbif ids corresponding to the - offsets defined in property: qcom,sde-vbif-off. -- qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit -- qcom,sde-vbif-default-ot-wr-limit: A u32 value indicates the default write OT limit -- qcom,sde-vbif-dynamic-ot-rd-limit: A series of 2 cell property, with a format - of (pps, OT limit), where pps is pixel per second and - OT limit is the read limit to apply if the given - pps is not exceeded. -- qcom,sde-vbif-dynamic-ot-wr-limit: A series of 2 cell property, with a format - of (pps, OT limit), where pps is pixel per second and - OT limit is the write limit to apply if the given - pps is not exceeded. -- qcom,sde-vbif-memtype-0: Array of u32 vbif memory type settings, group 0 -- qcom,sde-vbif-memtype-1: Array of u32 vbif memory type settings, group 1 -- qcom,sde-wb-id: Array of writeback ids corresponding to the - offsets defined in property: qcom,sde-wb-off. -- qcom,sde-wb-clk-ctrl: Array of 2 cell property describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-wb-off -- qcom,sde-wb-clk-status: Array of 2 cell property describing clk status - offsets for clock active state. 1st value - in the array represents offset of the status - register. 2nd value represents bit offset within - status register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-wb-off -- qcom,sde-reg-dma-off: Array of u32 offset addresses of the dma hardware blocks, - relative to "regdma_phys" defined in reg property. -- qcom,sde-reg-dma-id: Array of u32 DMA block type ids corresponding to the - offsets declared in property: qcom,sde-reg-dma-off -- qcom,sde-reg-dma-version: Version of the reg dma hardware blocks. -- qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys" - defined in reg property. -- qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast - functionality in the register dma hardware block should be used. -- qcom,sde-reg-dma-xin-id: VBIF clients id (xin) corresponding - to the LUTDMA block. -- qcom,sde-reg-dma-clk-ctrl: Array of 2 cell property describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. -- qcom,sde-dram-channels: This represents the number of channels in the - Bus memory controller. -- qcom,sde-num-nrt-paths: Integer property represents the number of non-realtime - paths in each Bus Scaling Usecase. This value depends on - number of AXI ports that are dedicated to non-realtime VBIF - for particular chipset. - These paths must be defined after rt-paths in - "qcom,msm-bus,vectors-KBps" vector request. -- qcom,sde-max-bw-low-kbps: This value indicates the max bandwidth in Kbps - that can be supported without underflow. - This is a low bandwidth threshold which should - be applied in most scenarios to be safe from - underflows when unable to satisfy bandwidth - requirements. -- qcom,sde-max-bw-high-kbps: This value indicates the max bandwidth in Kbps - that can be supported without underflow in the - event where there is no VFE. - This is a high bandwidth threshold which can be - applied in scenarios where panel interface can - be more tolerant to memory latency such as - command mode panels. -- qcom,sde-core-ib-ff: A string entry indicating the fudge factor for - core ib calculation. -- qcom,sde-core-clk-ff: A string entry indicating the fudge factor for - core clock calculation. -- qcom,sde-min-core-ib-kbps: This u32 value indicates the minimum mnoc ib - vote in Kbps that can be reduced without hitting underflow. - BW calculation logic will choose the IB bandwidth requirement - based on usecase if this floor value is not defined. -- qcom,sde-min-llcc-ib-kbps: This u32 value indicates the minimum llcc ib - vote in Kbps that can be reduced without hitting underflow. - BW calculation logic will choose the IB bandwidth requirement - based on usecase if this floor value is not defined. -- qcom,sde-min-dram-ib-kbps: This u32 value indicates the minimum dram ib - vote in Kbps that can be reduced without hitting underflow. - BW calculation logic will choose the IB bandwidth requirement - based on usecase if this floor value is not defined. -- qcom,sde-comp-ratio-rt: A string entry indicating the compression ratio - for each supported compressed format on realtime interface. - The string is composed of one or more of - /// - separated with spaces. -- qcom,sde-comp-ratio-nrt: A string entry indicating the compression ratio - for each supported compressed format on non-realtime interface. - The string is composed of one or more of - /// - separated with spaces. -- qcom,sde-undersized-prefill-lines: A u32 value indicates the size of undersized prefill in lines. -- qcom,sde-xtra-prefill-lines: A u32 value indicates the extra prefill in lines. -- qcom,sde-dest-scale-prefill-lines: A u32 value indicates the latency of destination scaler in lines. -- qcom,sde-macrotile-prefill-lines: A u32 value indicates the latency of macrotile in lines. -- qcom,sde-yuv-nv12-prefill-lines: A u32 value indicates the latency of yuv/nv12 in lines. -- qcom,sde-linear-prefill-lines: A u32 value indicates the latency of linear in lines. -- qcom,sde-downscaling-prefill-lines: A u32 value indicates the latency of downscaling in lines. -- qcom,sde-max-per-pipe-bw-kbps: Array of u32 value indicates the max per pipe bandwidth in Kbps. -- qcom,sde-amortizable-threshold: This value indicates the min for traffic shaping in lines. -- qcom,sde-vbif-qos-rt-remap: This u32 array is used to program vbif qos remapper register - priority for realtime clients. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-nrt-remap: This u32 array is used to program vbif qos remapper register - priority for non-realtime clients. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-cwb-remap: This u32 array is used to program vbif qos remapper register - priority for concurrent writeback clients. First 8 entries are - for rp_remap and the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-lutdma-remap: This u32 array is used to program vbif qos remapper register - priority for lutdma client. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-cnoc-remap: This u32 array is used to program vbif qos remapper register - priority for cnoc clients. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-offline-wb-remap: This u32 array is used to program vbif qos remapper register - priority for offline-wb clients. First 8 entries are for rp_remap - and the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-wb-rot-remap: This u32 array is used to program vbif qos remapper register - priority for wb-rotation clients. First 8 entries are for rp_remap - and the next 8 entries are for lvl_remap. -- qcom,sde-qos-refresh-rates: This u32 array indicates danger, safe and creq luts - qos configuration for different refresh rates. -- qcom,sde-danger-lut: This u32 array of 18 cell property, with a format of - for each entry, - , indicating the danger luts on sspp and wb. -- qcom,sde-safe-lut: This u32 array of 18 cell property, with a format of - for each entry, - , indicating the safe luts on sspp and wb. -- qcom,sde-creq-lut: This u64 array of 18 cell property, with a format of - for each - entry, for qos cases from , with of-node count based - on the qos refresh rates count. -- qcom,sde-cdp-setting: Array of 2 cell property, with a format of - for cdp use cases in - order of , and . -- qcom,sde-qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask. -- qcom,sde-qos-cpu-mask-performance: Each bit represents a CPU mask. For example - 0xf represents 4 cpu cores. These cores can be - silver or gold or gold+. -- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. -- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. -- qcom,sde-soccp-controller: The phandle for the soccp controller. - This value is optional and only required for targets with SOCCP. -- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. -- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used - for ipcc registers access. -- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg - offset. -- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline - rotation. -- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, - namely sspp or wb. Number of entries should match - the number of xin-ids defined in - property: qcom,sde-inline-rot-xin -- qcom,sde-inline-rot-clk-ctrl: Array of offsets describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. Number of offsets defined should - match the number of xin-ids defined in - property: qcom,sde-inline-rot-xin -- qcom,sde-secure-sid-mask: Array of secure SID masks used during - secure-camera/secure-display usecases. -- #power-domain-cells: Number of cells in a power-domain specifier and should contain 0. -- #list-cells: Number of mdp cells, must be 1. -- qcom,sde-mixer-display-pref: A string array indicating the preferred display type - for the mixer block. Possible values: - "primary" - preferred for primary display - "none" - no preference on display -- qcom,sde-mixer-cwb-pref: A string array indicating the preferred mixer block. - for CWB. Possible values: - "cwb" - preferred for cwb - "none" - no preference on display -- qcom,sde-mixer-dcwb-pref: A string array indicating the preferred mixer block. - for Dedicated-CWB. Possible values: - "dcwb" - preferred for dedicated-cwb - "none" - no preference on display -- qcom,sde-ctl-display-pref: A string array indicating the preferred display type - for the ctl block. Possible values: - "primary" - preferred for primary display - "none" - no preference on display -- qcom,sde-pipe-order-version: A u32 property to indicate version of pipe - ordering block - 0: lower priority pipe has to be on the left for a given pair of pipes. - 1: priority have to be explicitly configured for a given pair of pipes. -- qcom,sde-trusted-vm-env: Boolean property to indicate if the device - driver is executing in a trusted VM -- qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum - number of concurrent displays supported in the - trusted vm environment -- qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which - should be excluded from IO memory validation list - in trusted vm environment -- qcom,tvm-include-reg An array of u32 tuplets indicating the address - ranges of the display sub-device registers -- qcom,vram-size: A u32 value indicating the size of the VRAM in bytes -- qcom,pmic-arb-address: A u32 array of display related SPMI address - bit mask, which is a combination of SID and pheripheral id's. -- qcom,sde-ib-bw-vote: A u32 array of IB bandwidth vote values in kbps for - MNOC, LLCC and DDR/EBI respectively. -- qcom,sde-dnsc-blur-version: A u32 value indicating the downscale blur version -- qcom,sde-dnsc-blur-off: An array of u32 values with the offset for the downscale blur - block, from the "mdp_phys". -- qcom,sde-dnsc-blur-size: A u32 value indicates the downscale blur block address range. -- qcom,sde-dnsc-blur-gaus-lut-off: An array of u32 values with the offset for gaussian LUT - block, from the dnsc-blur-off -- qcom,sde-dnsc-blur-gaus-lut-size: A u32 value indicates the gaussian LUT block address range. -- qcom,sde-dnsc-blur-dither-off: An array of u32 values with the offset for dither - block, from the dnsc-blur-off -- qcom,sde-dnsc-blur-dither-size: A u32 value indicates the dither block address range. - -Bus Scaling: -- interconnects An array of 4 cell properties with the format of - (src-noc master-id dst-noc slave-id) as described in: - Documentation/devicetree/bindings/interconnect/interconnect.txt - One entry for each interconnect path available. - Master/Slave ID bindings can be found at: - include/dt-bindings/interconnect/ -- interconnect-names An array of string properties associated with "interconnects" - each with a unique name used to lookup the respective path. - The following paths are currently supported: qcom,sde-reg-bus, - qcom,sde-data-bus0, qcom,sde-data-bus1, qcom,sde-llcc-bus, - qcom,sde-ebi-bus -- qcom,sde-reg-bus,vectors-KBps:A series of 2 cell properties with a format of - (ab, ib) specified in kilobytes-per-second. - Used when applying reg-bus votes and must be - given whenever "qcom,sde-reg-bus" is used. -- qcom,sde-inline-rotator: A 2 cell property, with format of (rotator phandle, - instance id), of inline rotator device. - -SMMU Subnodes: -- smmu_sde_****: Child nodes representing sde smmu virtual - devices - -Subnode properties: -- compatible: Compatible names used for smmu devices. - names should be: - "qcom,smmu_sde_unsec": smmu context bank device - for unsecure sde real time domain. - "qcom,smmu_sde_sec": smmu context bank device - for secure sde real time domain. - "qcom,smmu_sde_nrt_unsec": smmu context bank device - for unsecure sde non-real time domain. - "qcom,smmu_sde_nrt_sec": smmu context bank device - for secure sde non-real time domain. - - -Please refer to ../../interrupt-controller/interrupts.txt for a general -description of interrupt bindings. - -Example: - mdss_mdp: qcom,mdss_mdp@900000 { - compatible = "qcom,sde-kms"; - reg = <0x00900000 0x90000>, - <0x009b0000 0x1040>, - <0x009b8000 0x1040>, - <0x0aeac000 0x00f0>; - reg-names = "mdp_phys", - "vbif_phys", - "vbif_nrt_phys", - "regdma_phys"; - qcom,tvm-include-reg = <0xaf20000 0x4d68>, - <0xaf30000 0x3fd4>; - clocks = <&clock_mmss clk_mdss_ahb_clk>, - <&clock_mmss clk_mdss_axi_clk>, - <&clock_mmss clk_mdp_clk_src>, - <&clock_mmss clk_mdss_mdp_vote_clk>, - <&clock_mmss clk_smmu_mdp_axi_clk>, - <&clock_mmss clk_mmagic_mdss_axi_clk>, - <&clock_mmss clk_mdss_vsync_clk>; - clock-names = "iface_clk", - "bus_clk", - "core_clk_src", - "core_clk", - "iommu_clk", - "mmagic_clk", - "vsync_clk"; - clock-rate = <0>, <0>, <0>; - clock-max-rate= <0 320000000 0>; - clock-mmrm = <0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0 0 0>; - mmagic-supply = <&gdsc_mmagic_mdss>; - vdd-supply = <&gdsc_mdss>; - interrupt-parent = <&intc>; - interrupts = <0 83 0>; - interrupt-controller; - #interrupt-cells = <1>; - iommus = <&mdp_smmu 0>; - #power-domain-cells = <0>; - - qcom,sde-hw-version = <0x70000000>; - qcom,hw-fence-sw-version = <0x1>; - qcom,sde-emulated-env; - qcom,sde-off = <0x1000>; - qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 - 0x00002600 0x00002800>; - qcom,sde-ctl-display-pref = "primary", "none", "none", - "none", "none"; - qcom,sde-mixer-off = <0x00045000 0x00046000 - 0x00047000 0x0004a000>; - qcom,sde-mixer-display-pref = "primary", "none", - "none", "none"; - qcom,sde-mixer-cwb-pref = "none", "none", - "cwb", "none"; - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-off = <0x00055000 0x00057000>; - qcom,sde-dspp-ad-off = <0x24000 0x22800>; - qcom,sde-dspp-ad-version = <0x00030000>; - qcom,sde-dspp-rc-version = <0x00010000>; - qcom,sde-dspp-rc-off = <0x15800 0x14c00>; - qcom,sde-dspp-rc-size = <0x100>; - qcom,sde-dspp-rc-min-region-width = <20>; - qcom,sde-dspp-spr-off = <0x15400 0x14400>; - qcom,sde-dspp-spr-size = <0x200>; - qcom,sde-dspp-spr-version = <0x00010000>: - qcom,sde-dspp-demura-off = <0x15600 0x14800>; - qcom,sde-dspp-demura-size = <0x200>; - qcom,sde-dspp-demura-version = <0x00010000>; - qcom,sde-lm-noise-off = <0x320>; - qcom,sde-lm-noise-version = <0x00010000>; - - qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>; - qcom,sde-dspp-aiqe-version = <0x00010000>; - qcom,sde-dspp-aiqe-size = <0x3fc>; - - qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>; - qcom,sde-dspp-aiqe-dither-version = <0x00010000>; - qcom,sde-dspp-aiqe-dither-size = <0x20>; - - qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>; - qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>; - qcom,sde-dspp-aiqe-wrapper-size = <0x1c>; - - qcom,sde-aiqe-has-feature-mdnie; - qcom,sde-aiqe-has-feature-abc; - qcom,sde-aiqe-has-feature-ssrc; - qcom,sde-aiqe-has-feature-copr; - - qcom,sde-dspp-rc-mem-size = <2720>; - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-wb-off = <0x00066000>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-intf-off = <0x0006b000 0x0006b800 - 0x0006c000 0x0006c800>; - qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi"; - qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; - qcom,sde-pp-off = <0x00071000 0x00071800 - 0x00072000 0x00072800>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; - qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; - qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; - qcom,sde-cdm-off = <0x0007a200>; - qcom,sde-dsc-off = <0x00081000 0x00081400>; - qcom,sde-vdc-off = <0x7C000>; - qcom,sde-vdc-size = <0xf10>; - qcom,sde-vdc-hw-rev = "vdc_1_2"; - qcom,sde-vdc-enc = <0x200>; - qcom,sde-vdc-ctl = <0xf00>; - qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; - - qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>; - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0 0xf8 0x110>; - - qcom,sde-qdss-off = <0x81a00>; - - qcom,sde-sspp-type = "vig", "vig", "vig", - "vig", "rgb", "rgb", - "rgb", "rgb", "dma", - "dma", "cursor", "cursor"; - - qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000 - 0x0000b000 0x00015000 0x00017000 - 0x00019000 0x0001b000 0x00025000 - 0x00027000 0x00035000 0x00037000>; - - qcom,sde-sspp-xin-id = <0 4 8 - 12 1 5 - 9 13 2 - 10 7 7>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, - <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, - <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, - <0x3b0 16>; - qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, - <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, - <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, - <0x3b0 16>; - qcom,sde-scaling-linewidth = <2560>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <2560>; - qcom,sde-mixer-blendstages = <0x7>; - qcom,sde-dsc-linewidth = <2048>; - qcom,sde-highest-bank-bit = <0x7 0x2>; - qcom,sde-ubwc-version = <0x10000000>; - qcom,sde-ubwc-static = <0x100>; - qcom,sde-ubwc-swizzle = <0>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-smart-panel-align-mode = <0xd>; - qcom,sde-panic-per-pipe; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-sspp-src-size = <0x100>; - qcom,sde-mixer-size = <0x100>; - qcom,sde-ctl-size = <0x100>; - qcom,sde-dspp-top-size = <0xc>; - qcom,sde-dspp-size = <0x100>; - qcom,sde-intf-size = <0x100>; - qcom,sde-dsc-size = <0x100>; - qcom,sde-cdm-size = <0x100>; - qcom,sde-pp-size = <0x100>; - qcom,sde-wb-size = <0x100>; - qcom,sde-dest-scaler-top-size = <0xc>; - qcom,sde-dest-scaler-size = <0x800>; - qcom,sde-len = <0x100>; - qcom,sde-wb-linewidth = <2560>; - qcom,sde-wb-linewidth-linear = <5120>; - qcom,sde-sspp-scale-size = <0x100>; - qcom,sde-mixer-blendstages = <0x8>; - qcom,sde-qseed-sw-lib-rev = "qseedv2"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-highest-bank-bit = <15>; - qcom,sde-has-mixer-gc; - qcom,sde-has-idle-pc; - qcom,sde-wakeup-with-touch; - qcom,fullsize-va-map; - qcom,sde-has-dest-scaler; - qcom,sde-max-trusted-vm-displays = <1>; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-sspp-max-rects = <1 1 1 1 - 1 1 1 1 - 1 1 - 1 1>; - qcom,sde-sspp-excl-rect = <1 1 1 1 - 1 1 1 1 - 1 1 - 1 1>; - qcom,sde-sspp-smart-dma-priority = <0 0 0 0 - 0 0 0 0 - 0 0 - 1 2>; - qcom,sde-smart-dma-rev = "smart_dma_v2"; - qcom,sde-te-off = <0x100>; - qcom,sde-te2-off = <0x100>; - qcom,sde-te-size = <0xffff>; - qcom,sde-te2-size = <0xffff>; - qcom,sde-trusted-vm-env; - - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-wb-clk-status = <0x3bc 20>; - - qcom,sde-qos-refresh-rates = <60 120>; - qcom,sde-danger-lut = <0x3ffff 0x3ffff 0x0 0x0 0x0 0x3fffff 0x3fffff>, - <0x3ffffff 0x3ffffff 0x0 0x0 0x0 0x3ffffff 0x3fffff, - 0xffff0000 0xffff0000>; - qcom,sde-safe-lut = <0xFE00 0xFE00 0xFFFF 0x01 0x03FF 0xF800 0xF800>, - <0xE000 0xE000 0xFFFF 0x01 0x03FF 0xE000 0xF800, 0xff, - 0xff>; - qcom,sde-creq-lut = <0x00112234 0x45566777 0x00112236 0x67777777 - 0x00112234 0x45566777 0x00112236 0x67777777 - 0x0 0x0 0x0 0x0 - 0x77776666 0x66666540 0x77776666 0x66666540 - 0x77776541 0x00000000 0x77776541 0x00000000 - 0x00123445 0x56677777 0x00123667 0x77777777 - 0x00123445 0x56677777 0x00123667 0x77777777 - 0x55555544 0x33221100 0x55555544 0x33221100>, - <0x02344455 0x56667777 0x02366677 0x77777777 - 0x02344455 0x56667777 0x02366677 0x77777777 - 0x0 0x0 0x0 0x0 - 0x77776666 0x66666540 0x77776666 0x66666540 - 0x77776541 0x00000000 0x77776541 0x00000000 - 0x02344455 0x56667777 0x02366677 0x77777777 - 0x00123445 0x56677777 0x00123667 0x77777777 - 0x55555544 0x33221100 0x55555544 0x33221100>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-mask-performance = <0xf>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - qcom,sde-soccp-controller = <&soccp_pas>; - qcom,sde-ipcc-protocol-id = <0x2>; - qcom,sde-ipcc-client-dpu-phys-id = <0x19>; - qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; - - qcom,sde-vbif-off = <0 0>; - qcom,sde-vbif-id = <0 1>; - qcom,sde-vbif-default-ot-rd-limit = <32>; - qcom,sde-vbif-default-ot-wr-limit = <16>; - qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>, - <124416000 4>, <248832000 16>; - qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>, - <124416000 4>, <248832000 16>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <1>; - - qcom,sde-max-bw-high-kbps = <9000000>; - qcom,sde-max-bw-low-kbps = <9000000>; - - qcom,sde-core-ib-ff = "1.1"; - qcom,sde-core-clk-ff = "1.0"; - qcom,sde-min-core-ib-kbps = <2400000>; - qcom,sde-min-llcc-ib-kbps = <800000>; - qcom,sde-min-dram-ib-kbps = <800000>; - qcom,sde-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; - qcom,sde-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; - qcom,sde-undersized-prefill-lines = <4>; - qcom,sde-xtra-prefill-lines = <5>; - qcom,sde-dest-scale-prefill-lines = <6>; - qcom,sde-macrotile-prefill-lines = <7>; - qcom,sde-yuv-nv12-prefill-lines = <8>; - qcom,sde-linear-prefill-lines = <9>; - qcom,sde-downscaling-prefill-lines = <10>; - qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000 - 2400000 2400000 2400000 2400000>; - qcom,sde-amortizable-threshold = <11>; - qcom,sde-secure-sid-mask = <0x200801 0x200c01>; - - qcom,sde-dnsc-blur-version = <0x100>; - qcom,sde-dnsc-blur-off = <0x7D000>; - qcom,sde-dnsc-blur-size = <0x40>; - qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; - qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; - qcom,sde-dnsc-blur-dither-off = <0x5E0>; - qcom,sde-dnsc-blur-dither-size = <0x20>; - - qcom,vram-size = <0x200000>; - qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; - - qcom,sde-ib-bw-vote = <2500000 0 800000>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6 3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3 3 3 4 4 5 5 6 3>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4 3 3 3 3 4 4 4 4>; - qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; - - qcom,sde-reg-dma-off = <0 0x400>; - qcom,sde-reg-dma-id = <0 1>; - qcom,sde-reg-dma-version = <0x00020000>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-broadcast-disabled = <0>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - nvmem-cells = <&ssip_config>; - nvmem-cell-names = "ssip_config"; - - qcom,sde-sspp-vig-blocks { - vcm@0 { - cell-index = <0>; - qcom,sde-vig-top-off = <0xa00>; - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xe0>; - qcom,sde-vig-gamut = <0x1d00 0x00060001>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; - /* Offset from vig top, version of HSIC */ - qcom,sde-vig-hsic = <0x200 0x00010000>; - qcom,sde-vig-memcolor = <0x200 0x00010000>; - qcom,sde-vig-pcc = <0x1780 0x00010000>; - qcom,sde-vig-inverse-pma; - qcom,sde-fp16-igc = <0x200 0x00010000>; - qcom,sde-fp16-unmult = <0x200 0x00010000>; - qcom,sde-fp16-gc = <0x200 0x00010000>; - qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x700 0x00010000>; - qcom,sde-ucsc-unmult = <0x700 0x00010000>; - qcom,sde-ucsc-gc = <0x700 0x00010000>; - qcom,sde-ucsc-csc = <0x700 0x00010000>; - qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; - }; - - vcm@1 { - cell-index = <1>; - qcom,sde-fp16-igc = <0x280 0x00010000>; - qcom,sde-fp16-unmult = <0x280 0x00010000>; - qcom,sde-fp16-gc = <0x280 0x00010000>; - qcom,sde-fp16-csc = <0x280 0x00010000>; - qcom,sde-ucsc-igc = <0x1700 0x00010000>; - qcom,sde-ucsc-unmult = <0x1700 0x00010000>; - qcom,sde-ucsc-gc = <0x1700 0x00010000>; - qcom,sde-ucsc-csc = <0x1700 0x00010000>; - qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; - }; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - cell-index = <0>; - qcom,sde-dma-top-off = <0x800>; - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - qcom,sde-fp16-igc = <0x200 0x00010000>; - qcom,sde-fp16-unmult = <0x200 0x00010000>; - qcom,sde-fp16-gc = <0x200 0x00010000>; - qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x700 0x00010000>; - qcom,sde-ucsc-unmult = <0x700 0x00010000>; - qcom,sde-ucsc-gc = <0x700 0x00010000>; - qcom,sde-ucsc-csc = <0x700 0x00010000>; - qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; - }; - - dgm@1 { - cell-index = <1>; - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - qcom,sde-fp16-igc = <0x200 0x00010000>; - qcom,sde-fp16-unmult = <0x200 0x00010000>; - qcom,sde-fp16-gc = <0x200 0x00010000>; - qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x1700 0x00010000>; - qcom,sde-ucsc-unmult = <0x1700 0x00010000>; - qcom,sde-ucsc-gc = <0x1700 0x00010000>; - qcom,sde-ucsc-csc = <0x1700 0x00010000>; - qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; - }; - }; - - qcom,sde-sspp-rgb-blocks { - qcom,sde-rgb-scaler-off = <0x200>; - qcom,sde-rgb-scaler-size = <0x74>; - qcom,sde-rgb-pcc = <0x380 0x00010000>; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00010000>; - qcom,sde-dspp-pcc = <0x1700 0x00010000>; - qcom,sde-dspp-gc = <0x17c0 0x00010000>; - qcom,sde-dspp-hsic = <0x0 0x00010000>; - qcom,sde-dspp-memcolor = <0x0 0x00010000>; - qcom,sde-dspp-sixzone = <0x0 0x00010000>; - qcom,sde-dspp-gamut = <0x1600 0x00010000>; - qcom,sde-dspp-dither = <0x0 0x00010000>; - qcom,sde-dspp-hist = <0x0 0x00010000>; - qcom,sde-dspp-vlut = <0x0 0x00010000>; - }; - - qcom,sde-mixer-blocks { - qcom,sde-mixer-gc = <0x3c0 0x00010000>; - }; - - qcom,msm-hdmi-audio-rx { - compatible = "qcom,msm-hdmi-audio-codec-rx"; - }; - - qcom,sde-inline-rotator = <&mdss_rotator 0>; - qcom,sde-inline-rot-xin = <10 11>; - qcom,sde-inline-rot-xin-type = "sspp", "wb"; - qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <0>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - }; - - interconnects = <&mmss_noc MASTER_MDP0 &mmss_noc SLAVE_MNOC_HF_MEM_NOC> - <&mmss_noc MASTER_MDP1 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>, - <&gem_noc MASTER_MNOC_HF_MEM_NOC &gem_noc SLAVE_LLCC>, - <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-llcc-bus", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 76800>, - <0 150000>, - <0 300000>; - - smmu_kms_unsec: qcom,smmu_kms_unsec_cb { - compatible = "qcom,smmu_sde_unsec"; - iommus = <&mmss_smmu 0>; - }; - - smmu_kms_sec: qcom,smmu_kms_sec_cb { - compatible = "qcom,smmu_sde_sec"; - iommus = <&mmss_smmu 1>; - }; - }; diff --git a/bindings/sde.yaml b/bindings/sde.yaml new file mode 100644 index 00000000..8f7361bc --- /dev/null +++ b/bindings/sde.yaml @@ -0,0 +1,2076 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SDE KMS + +maintainers: + - Veera Sundaram Sankaran + - Kalyan Thota + - Ravi Teja Tamatam + - Jatin Srivastava + +description: | + Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user + interface to different panel interfaces. SDE driver is the core of + display subsystem which manage all data paths to different panel interfaces + Please refer to ../../interrupt-controller/interrupts.txt for a general + description of interrupt bindings. + +properties: + compatible: + const: qcom,sde-kms + + qcom,msm-hdmi-audio-rx: + type: object + compatible: + const: qcom,msm-hdmi-audio-codec-rx + + reg: + description: | + Offset and length of the register set for the device.Base address and length of DP hardware's + memory mapped regions. + + reg-names: + description: Names to refer to register sets related to this device + $ref: /schemas/types.yaml#/definitions/string-array + + clocks: + description: List of Phandles for clock device nodes needed by the device. + + clock-names: + description: List of clock names needed by the device. + $ref: /schemas/types.yaml#/definitions/string-array + + mmagic-supply: + description: Phandle for mmagic mdss supply regulator device node. + $ref: /schemas/types.yaml#/definitions/phandle + + vdd-supply: + description: Phandle for vdd regulator device node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupt-parent: + description: Must be core interrupt controller. + + interrupts: + description: Interrupt associated with MDSS. + + interrupt-controller: + description: Mark the device node as an interrupt controller. + + '#interrupt-cells': + description: Should be one. The first cell is interrupt number. + + iommus: + description: Specifies the SID's used by this context bank. + + qcom,sde-sspp-type: + description: | + Array of strings for SDE source surface pipes type information. + A source pipe can be "vig", "rgb", "dma" or "cursor" type. + Number of xin ids defined should match the number of offsets + defined in property: qcom,sde-sspp-off. + $ref: /schemas/types.yaml#/definitions/string-array + enum: [vig, rgb, dma, cursor] + + qcom,sde-sspp-off: + description: | + Array of offset for SDE source surface pipes. The offsets + are calculated from register "mdp_phys" defined in + reg property + "sde-off". The number of offsets defined here should + reflect the amount of pipes that can be active in SDE for + this configuration. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-xin-id: + description: | + Array of VBIF clients ids (xins) corresponding + to the respective source pipes. Number of xin ids + defined should match the number of offsets + defined in property: qcom,sde-sspp-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-ctl-off: + description: | + Array of offset addresses for the available ctl + hw blocks within SDE, these offsets are + calculated from register "mdp_phys" defined in + reg property. The number of ctl offsets defined + here should reflect the number of control paths + that can be configured concurrently on SDE for + this configuration. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-wb-off: + description: | + Array of offset addresses for the programmable + writeback blocks within SDE. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-wb-xin-id: + description: | + Array of VBIF clients ids (xins) corresponding + to the respective writeback. Number of xin ids + defined should match the number of offsets + defined in property: qcom,sde-wb-off.. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-mixer-off: + description: | + Array of offset addresses for the available + mixer blocks that can drive data to panel + interfaces. These offsets are be calculated from + register "mdp_phys" defined in reg property. + The number of offsets defined should reflect the + amount of mixers that can drive data to a panel + interface. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-top-off: + description: | + Offset address for the dspp top block. + The offset is calculated from register "mdp_phys" + defined in reg property. + + qcom,sde-dspp-off: + description: | + Array of offset addresses for the available dspp + blocks. These offsets are calculated from + register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-pp-off: + description: | + Array of offset addresses for the available + pingpong blocks. These offsets are calculated + from register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-pp-slave: + description: | + Array of flags indicating whether each ping pong + block may be configured as a pp slave. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-pp-merge-3d-id: + description: | + Array of index ID values for the merge 3d block + connected to each pingpong, starting at 0. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-merge-3d-off: + description: | + Array of offset addresses for the available + merge 3d blocks. These offsets are calculated + from register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-intf-off: + description: | + Array of offset addresses for the available SDE + interface blocks that can drive data to a + panel controller. The offsets are calculated + from "mdp_phys" defined in reg property. The number + of offsets defined should reflect the number of + programmable interface blocks available in hardware. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-mixer-blend-op-off: + description: | + Array of offset addresses for the available + blending stages. The offsets are relative to + qcom,sde-mixer-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-mixer-pair-mask: + description: | + Array of mixer numbers that can be paired with + mixer number corresponding to the array index. + $ref: /schemas/types.yaml#/definitions/uint32-array + + clock-rate: + description: List of clock rates in Hz. + + clock-max-rate: + description: List of maximum clock rate in Hz that this device supports. + + clock-mmrm: + description: | + List of clocks that enable setting the clk rate through MMRM driver. + The order of the list must match the 'clocks' and 'clock-names' properties. + The 'DISP_CC' ID of the clock must be used to enable the property for the + respective clock, whereas a value of zero disables the property. + + qcom,platform-supply-entries: + description: | + A node that lists the elements of the supply. There + can be more than one instance of this binding, + in which case the entry would be appended with + the supply entry index. + e.g. qcom,platform-supply-entry@0 + type: object + patternProperties: + "qcom,platform\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-hw-version: + description: A u32 value indicates the MDSS hw version + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hw-fence-sw-version: + description: | + A u32 value to indicate the hw fencing version. If set to a value + greather than zero, driver will attempt to enable the feature (if + supported by the HW). Otherwise, if this value is not set or set + to zero, feature will remain disabled. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-src-size: + description: A u32 value indicates the address range for each sspp. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-size: + description: A u32 value indicates the address range for each mixer. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ctl-size: + description: A u32 value indicates the address range for each ctl. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-size: + description: A u32 value indicates the address range for each dspp. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-intf-size: + description: A u32 value indicates the address range for each intf. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-size: + description: A u32 value indicates the address range for each dsc. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-size: + description: A u32 value indicates the address range for each vdc. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-cdm-size: + description: A u32 value indicates the address range for each cdm. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-pp-size: + description: A u32 value indicates the address range for each pingpong. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-merge-3d-size: + description: A u32 value indicates the address range for each merge 3d. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-pp-cwb: + description: | + Array of u32 flags indicating whether each ping pong + block may be configured as a cwb pp block. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-wb-size: + description: A u32 value indicates the address range for each writeback. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-len: + description: A u32 entry for SDE address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-intf-max-prefetch-lines: + description: Array of u32 values for max prefetch lines on each interface. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-linewidth: + description: A u32 value indicates the max sspp line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vig-sspp-linewidth: + description: A u32 value indicates the max vig sspp line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-scaling-linewidth: + description: A u32 value indicates the max vig source pipe line width for scaling purposes. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-linewidth: + description: A u32 value indicates the max mixer line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-wb-linewidth: + description: A u32 value indicates the max writeback line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-wb-linewidth-linear: + description: A u32 value indicates the max line width supported by WB for linear color formats. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-scale-size: + description: A u32 value indicates the scaling block size on sspp. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-blendstages: + description: A u32 value indicates the max mixer blend stages for alpha blending. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qseed-sw-lib-rev: + description: | + A string entry indicates qseed sw library revision + supporting the qseed HW block. It supports + "qseedv3", "qseedv3lite" and "qseedv2" entries for qseed + revision. By default "qseedv2" is used if this + optional property is not defined. + $ref: /schemas/types.yaml#/definitions/string-array + default: qseedv2 + + qcom,sde-qseed-scalar-version: + description: A u32 value indicating the HW version of the QSEED hardware block. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-csc-type: + description: | + A string entry indicates csc support on sspp and wb. + It supports "csc" and "csc-10bit" entries for csc + type. + $ref: /schemas/types.yaml#/definitions/string-array + enum: [csc, csc-10bit] + + qcom,sde-highest-bank-bit: + description: | + Property to specify GPU/Camera/Video highest memory + bank bit used for tile format buffers. First value + in the array represents the ddr type and the second + value is the hbb value corresponding to the ddr type. + + qcom,sde-ubwc-version: + description: | + Property to specify the UBWC feature version. A u32 UBWC version is based on + MDSS support. + + qcom,sde-ubwc-static: + description: Property to specify the default UBWC static configuration value. + + qcom,sde-ubwc-bw-calc-version: + description: A u32 property to specify version of UBWC bandwidth calculation algorithm + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ubwc-swizzle: + description: Property to specify the default UBWC swizzle configuration value. + + qcom,sde-smart-panel-align-mode: + description: | + A u32 property to specify the align mode for + split display on smart panel. Possible values: + 0x0 - no alignment + 0xc - align at start of frame + 0xd - align at start of line + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0x0, 0xc, 0xd] + + qcom,sde-panic-per-pipe: + description: | + Boolean property to indicate if panic signal control feature is available on each + source pipe. + + qcom,sde-has-src-split: + description: | + Boolean property to indicate if source split + feature is available or not. + + qcom,sde-has-dim-layer: + description: | + Boolean property to indicate if mixer has dim layer + feature is available or not. + + qcom,sde-has-idle-pc: + description: | + Boolean property to indicate if target has idle + power collapse feature available or not. + + qcom,sde-wakeup-with-touch: + description: | + Boolean property to indicate if command mode display + will exit from power collapse based on display input + touch event or not. + + qcom,sde-has-mixer-gc: + description: | + Boolean property to indicate if mixer has gamma correction + feature available or not. + + qcom,sde-has-dest-scaler: + description: | + Boolean property to indicate if destination scaler + feature is available or not. + + qcom,sde-max-dest-scaler-input-linewidth: + description: | + A u32 value indicates the + maximum input line width to destination scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-max-dest-scaler-output-linewidth: + description: | + A u32 value indicates the + maximum output line width of destination scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scaler-top-off: + description: | + A u32 value provides the + offset from mdp base to destination scaler block. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scaler-top-size: + description: A u32 value indicates the address range for ds top + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scaler-off: + description: | + Array of u32 offsets indicate the qseed3 scaler blocks + offset from destination scaler top offset. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dest-scaler-size: + description: A u32 value indicates the address range for each scaler block + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-clk-ctrl: + description: | + Array of offsets describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-sspp-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-clk-status: + description: | + Array of offsets describing clk status + offsets for clock active state. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + status register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-sspp-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-excl-rect: + description: | + Array of u32 values indicating exclusion rectangle + support on each sspp. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-smart-dma-priority: + description: | + Array of u32 values indicating hw pipe + priority of secondary rectangles when smart dma + is supported. Number of priority values should + match the number of offsets defined in + qcom,sde-sspp-off node. Zero indicates no support + for smart dma for the sspp. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-smart-dma-rev: + description: | + A string entry indicating the smart dma version + supported on the device. Supported entries are + "smart_dma_v1" and "smart_dma_v2". + $ref: /schemas/types.yaml#/definitions/string-array + enum: [smart_dma_v1, smart_dma_v2] + + qcom,sde-vdc-hw-rev: + description: A string indicating the hw version of vdc. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-intf-type: + description: | + Array of string provides the interface type information. + Possible string values + "dsi" - dsi display interface + "dp" - Display Port interface + "hdmi" - HDMI display interface + An interface is considered as "none" if interface type + is not defined. + $ref: /schemas/types.yaml#/definitions/string-array + default: none + enum: [dsi, dp, hdmi] + + qcom,sde-intf-tear-irq-off: + description: | + Array of offset addresses for the available + tear effect (TE) IRQ blocks from "mdp_phys". + There should be one entry per INTF instance with + a zero value for INTFs without TE IRQ block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-emulated-env: + description: | + Boolean property to indicate if the MDSS is running in an + emulated environment. + + qcom,sde-off: + description: SDE offset from "mdp_phys" defined in reg property. + + qcom,sde-cdm-off: + description: | + Array of offset addresses for the available + cdm blocks. These offsets will be calculated from + register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-off: + description: | + Array of offset addresses for the available + vbif blocks. These offsets will be calculated from + register "vbif_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-size: + description: A u32 value indicates the vbif block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-uidle-off: + description: | + A u32 value with the offset for the uidle block, from the "mdp_phys". + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-uidle-size: + description: A u32 value indicates the uidle block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te-off: + description: | + A u32 offset indicates the te block offset on pingpong. + This offset is 0x0 by default. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te2-off: + description: A u32 offset indicates the te2 block offset on pingpong. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te-size: + description: A u32 value indicates the te block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te2-size: + description: A u32 value indicates the te2 block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-off: + description: | + Array of offset addresses for the available dsc + blocks. These offsets are calculated from + register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-hw-rev: + description: A string value indicates the dsc hw block version. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-dsc-enc: + description: | + Array of offset addresses for the available dsc + encoder blocks. These offsets are calculated from + the corresponding DSC base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-enc-size: + description: A u32 value indicates the enc block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-ctl: + description: | + Array of offset addresses for the available dsc + ctl blocks. These offsets are calculated from + the corresponding DSC base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-ctl-size: + description: A u32 value indicates the ctl block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-native422-supp: + description: | + Array of flags indicating whether corresponding dsc + block can support native 422 and native 420 + encoding. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-linewidth: + description: A u32 value indicates the max dsc line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-off: + description: | + A u32 offset address for the available vdc blocks. + This offset is calculated from register "mdp_phys" + defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-enc-size: + description: A u32 value indicates the enc block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-enc: + description: | + A u32 offset address for the vdc encoder block. This offset is + calculated from qcom,sde-vdc-off. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-ctl: + description: | + A u32 offset address for the vdc ctl block. This offset is + calculated from qcom,sde-vdc-off. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-ctl-size: + description: A u32 value indicates the ctl block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qdss-off: + description: A u32 offset indicates the qdss block offset. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dither-off: + description: A u32 offset indicates the dither block offset on pingpong. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dither-version: + description: A u32 value indicates the dither block version. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dither-size: + description: A u32 value indicates the dither block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-cwb-dither: + description: | + Array of u32 flags indicating whether each dither block + may be configured as a cwb dither block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-vig-blocks: + description: | + A node that lists the blocks inside the VIG hardware. There can + be more than one instance of this binding, in which case the + entry would be appended with the vcm entry index. Each entry will + contain the offset and version (if needed) of each feature block. + The presence of a block entry indicates that the SSPP VIG contains + that feature hardware. Eg: vcm@0 + type: object + patternProperties: + "vcm@+\w": + properties: + cell-index: + description: A u32 index for the sub-block. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-top-off: + description: A u32 offset of the sub-block top. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-csc-off: + description: offset of CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-qseed-off: + description: offset of QSEED hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-qseed-size: + description: A u32 address range for qseed scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-pcc: + description: offset and version of PCC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-hsic: + description: offset and version of global PA adjustment + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-memcolor: + description: offset and version of PA memcolor hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-gamut: + description: offset and version of 3D LUT Gamut hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-igc: + description: offset and version of 1D LUT IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-inverse-pma: + description: | + Boolean property to indicate if inverse PMA feature is + available on VIG pipe + qcom,sde-fp16-igc: + description: u32 offset and version of the FP16 IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-unmult: + description: u32 offset and version of the FP16 Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-gc: + description: u32 offset and version of the FP16 GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-csc: + description: u32 offset and version of the FP16 CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-igc: + description: u32 offset and version of the UCSC IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-unmult: + description: u32 offset and version of the UCSC Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-gc: + description: u32 offset and version of the UCSC GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-csc: + description: u32 offset and version of the UCSC CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-alpha-dither: + description: u32 offset and version of the UCSC Alpha Dither hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-dma-blocks: + description: | + A node that lists the blocks inside the DMA hardware. There + can be more than one instance of this binding, in which case the + entry would be appended with dgm entry index. Each entry will + contain the offset and version (if needed) of each feature block. + The presence of a block entry indicates that the SSPP DMA contains + that feature hardware. + e.g. qcom,sde-sspp-dma-blocks + -- dgm@0 + type: object + patternProperties: + "dgm@+\w": + properties: + cell-index: + description: A u32 index for the sub-block. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-top-off: + description: A u32 offset of the sub-block top. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-igc: + description: offset and version of DMA IGC + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-gc: + description: offset and version of DMA GC + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-inverse-pma: + description: | + Boolean property to indicate if inverse PMA feature is + available on DMA pipe. + qcom,sde-dma-csc-off: + description: offset of CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-igc: + description: u32 offset and version of the FP16 IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-unmult: + description: u32 offset and version of the FP16 Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-gc: + description: u32 offset and version of the FP16 GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-csc: + description: u32 offset and version of the FP16 CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-igc: + description: u32 offset and version of the UCSC IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-unmult: + description: u32 offset and version of the UCSC Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-gc: + description: u32 offset and version of the UCSC GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-csc: + description: u32 offset and version of the UCSC CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-alpha-dither: + description: u32 offset and version of the UCSC Alpha Dither hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-rgb-blocks: + description: | + A node that lists the blocks inside the RGB hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the SSPP RGB contains that feature hardware. + e.g. qcom,sde-sspp-rgb-blocks + type: object + properties: + qcom,sde-rgb-scaler-off: + description: offset of RGB scaler hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-rgb-scaler-size: + description: A u32 address range for scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-rgb-pcc: + description: offset and version of PCC hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-blocks: + description: | + A node that lists the blocks inside the DSPP hardware. The + block entries will contain the offset and version of each + feature block. The presence of a block entry indicates that + the DSPP contains that feature hardware. + e.g. qcom,sde-dspp-blocks + type: object + properties: + qcom,sde-dspp-pcc: + description: offset and version of PCC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-gc: + description: offset and version of GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-igc: + description: offset and version of IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-hsic: + description: offset and version of global PA adjustment + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-memcolor: + description: offset and version of PA memcolor hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-sixzone: + description: offset and version of PA sixzone hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-gamut: + description: offset and version of Gamut mapping hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-dither: + description: offset and version of dither hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-hist: + description: offset and version of histogram hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-vlut: + description: offset and version of PA vLUT hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-blocks: + description: | + A node that lists the blocks inside the layer mixer hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the layer mixer contains that feature hardware. + e.g. qcom,sde-mixer-blocks + - qcom,sde-mixer-gc: offset and version of mixer GC hardware + + qcom,sde-dspp-ad-off: + description: | + Array of u32 offsets indicate the ad block offset from the + DSPP offset. Since AD hardware is represented as part of + DSPP block, the AD offsets must be offset from the + corresponding DSPP base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-ad-version: + description: A u32 value indicating the version of the AD hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-ltm-version: + description: | + A u32 value indicating the major(upper 16 bits) and minor(lower 16 bits) + version of the LTM hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-ltm-off: + description: | + Array of u32 offsets indicate the LTM block offsets from the + DSPP offsets. Since LTM hardware is represented as part of + DSPP block, the LTM offsets are calculated based on the + corresponding DSPP base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-rc-version: + description: A u32 value indicating the version of the RC hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-off: + description: | + Array of u32 offsets indicate the RC block offsets from the + DSPP offsets. Since RC hardware is represented as part of + DSPP block, the RC offsets are calculated based on the + corresponding DSPP base. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-size: + description: A u32 value indicating the RC block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-mem-size: + description: A u32 value indicating the RC block shared memory size. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-min-region-width: + description: A u32 value indicating the RC block minimum region width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-spr-off: + description: | + Array of u32 offsets indicate the SPR block offsets from the + corresponding DSPP block offset as base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-spr-size: + description: A u32 value indicating the SPR block register address range + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-spr-version: + description: A u32 value indicating the version of SPR hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-demura-off: + description: | + Array of u32 offsets indicate the demura block offsets from the + corresponding DSPP block offset as base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-demura-size: + description: A u32 value indicating the demura block register address range + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-demura-version: + description: A u32 value indicating the version of demura hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-off: + description: | + Array of u32 values indicating the offset of each AIQE block + relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-version: + description: A u32 value indicating the version of the AIQE hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-size: + description: | + A u32 value indicating the shared memory size of each AIQE + hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-dither-off: + description: | + Array of u32 values indicating the offset of each AIQE + dither block relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-dither-version: + description: A u32 value indicating the version of the AIQE dither hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-dither-size: + description: | + A u32 value indicating the shared memory size of each AIQE + dither hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-wrapper-off: + description: | + Array of u32 values indicating the offset of each AIQE + wrapper block relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-wrapper-version: + description: A u32 value indicating the version of the AIQE wrapper hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-wrapper-size: + description: | + A u32 value indicating the shared memory size of each AIQE + wrapper hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-aiscaler-off: + description: | + Array of u32 values indicating the offset of each AIQE + AI Scaler block relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-aiscaler-version: + description: A u32 value indicating the version of the AIQE AI Scaler hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-aiscaler-size: + description: | + A u32 value indicating the shared memory size of each AIQE + AI Scaler hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-aiqe-has-feature-mdnie: + description: Boolean property indicating the presence of AIQE feature mDNIe hardware. + + qcom,sde-aiqe-has-feature-abc: + description: Boolean property indicating the presence of AIQE feature ABC hardware. + + qcom,sde-aiqe-has-feature-ssrc: + description: Boolean property indicating the presence of AIQE feature SSRC hardware. + + qcom,sde-aiqe-has-feature-copr: + description: Boolean property indicating the presence of AIQE feature COPR hardware. + + qcom,sde-aiqe-has-feature-aiscaler: + description: Boolean property indicating the presence of AIQE feature AI Scaler hardware. + + qcom,sde-lm-noise-off: + description: A u32 value indicating noise layer offset from mixer base. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-lm-noise-version: + description: A u32 value indicating the noise layer version. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vbif-id: + description: | + Array of vbif ids corresponding to the + offsets defined in property: qcom,sde-vbif-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-default-ot-rd-limit: + description: A u32 value indicates the default read OT limit + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vbif-default-ot-wr-limit: + description: A u32 value indicates the default write OT limit + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vbif-dynamic-ot-rd-limit: + description: | + A series of 2 cell property, with a format + of (pps, OT limit), where pps is pixel per second and + OT limit is the read limit to apply if the given + pps is not exceeded. + + qcom,sde-vbif-dynamic-ot-wr-limit: + description: | + A series of 2 cell property, with a format + of (pps, OT limit), where pps is pixel per second and + OT limit is the write limit to apply if the given + pps is not exceeded. + + qcom,sde-vbif-memtype-0: + description: Array of u32 vbif memory type settings, group 0 + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-memtype-1: + description: Array of u32 vbif memory type settings, group 1 + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-wb-id: + description: | + Array of writeback ids corresponding to the + offsets defined in property: qcom,sde-wb-off. + + qcom,sde-wb-clk-ctrl: + description: | + Array of 2 cell property describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off + + qcom,sde-wb-clk-status: + description: | + Array of 2 cell property describing clk status + offsets for clock active state. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + status register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off + + qcom,sde-reg-dma-off: + description: | + Array of u32 offset addresses of the dma hardware blocks, + relative to "regdma_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-reg-dma-id: + description: | + Array of u32 DMA block type ids corresponding to the + offsets declared in property: qcom,sde-reg-dma-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-reg-dma-version: + description: Version of the reg dma hardware blocks. + + qcom,sde-reg-dma-trigger-off: + description: | + Offset of the lut dma trigger reg from "mdp_phys" + defined in reg property. + + qcom,sde-reg-dma-broadcast-disabled: + description: | + Boolean property to indicate if broadcast + functionality in the register dma hardware block should be used. + + qcom,sde-reg-dma-xin-id: + description: VBIF clients id (xin) corresponding to the LUTDMA block. + + qcom,sde-reg-dma-clk-ctrl: + description: | + Array of 2 cell property describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: offset of the control register + - description: bit offset within the control register + + qcom,sde-dram-channels: + description: This represents the number of channels in the Bus memory controller. + + qcom,sde-num-nrt-paths: + description: | + Integer property represents the number of non-realtime + paths in each Bus Scaling Usecase. This value depends on + number of AXI ports that are dedicated to non-realtime VBIF + for particular chipset. + These paths must be defined after rt-paths in + "qcom,msm-bus,vectors-KBps" vector request. + + qcom,sde-max-bw-low-kbps: + description: | + This value indicates the max bandwidth in Kbps + that can be supported without underflow. + This is a low bandwidth threshold which should + be applied in most scenarios to be safe from + underflows when unable to satisfy bandwidth + requirements. + + qcom,sde-max-bw-high-kbps: + description: | + This value indicates the max bandwidth in Kbps + that can be supported without underflow in the + event where there is no VFE. + This is a high bandwidth threshold which can be + applied in scenarios where panel interface can + be more tolerant to memory latency such as + command mode panels. + + qcom,sde-core-ib-ff: + description: A string entry indicating the fudge factor for core ib calculation. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-core-clk-ff: + description: | + A string entry indicating the fudge factor for + core clock calculation. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-min-core-ib-kbps: + description: | + This u32 value indicates the minimum mnoc ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-min-llcc-ib-kbps: + description: | + This u32 value indicates the minimum llcc ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-min-dram-ib-kbps: + description: | + This u32 value indicates the minimum dram ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-comp-ratio-rt: + description: | + A string entry indicating the compression ratio + for each supported compressed format on realtime interface. + The string is composed of one or more of + /// + separated with spaces. + + qcom,sde-comp-ratio-nrt: + description: | + A string entry indicating the compression ratio + for each supported compressed format on non-realtime interface. + The string is composed of one or more of + /// + separated with spaces. + + qcom,sde-undersized-prefill-lines: + description: A u32 value indicates the size of undersized prefill in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-xtra-prefill-lines: + description: A u32 value indicates the extra prefill in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scale-prefill-lines: + description: A u32 value indicates the latency of destination scaler in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-macrotile-prefill-lines: + description: A u32 value indicates the latency of macrotile in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-yuv-nv12-prefill-lines: + description: A u32 value indicates the latency of yuv/nv12 in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-linear-prefill-lines: + description: A u32 value indicates the latency of linear in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-downscaling-prefill-lines: + description: A u32 value indicates the latency of downscaling in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-max-per-pipe-bw-kbps: + description: Array of u32 value indicates the max per pipe bandwidth in Kbps. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-amortizable-threshold: + description: This value indicates the min for traffic shaping in lines. + + qcom,sde-vbif-qos-rt-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for realtime clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-nrt-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for non-realtime clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-cwb-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for concurrent writeback clients. First 8 entries are + for rp_remap and the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-lutdma-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for lutdma client. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-cnoc-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for cnoc clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-offline-wb-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for offline-wb clients. First 8 entries are for rp_remap + and the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-wb-rot-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for wb-rotation clients. First 8 entries are for rp_remap + and the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-qos-refresh-rates: + description: | + This u32 array indicates danger, safe and creq luts + qos configuration for different refresh rates. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-danger-lut: + description: | + This u32 array of 18 cell property, with a format of + for each entry, + , indicating the danger luts on sspp and wb. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-safe-lut: + description: | + This u32 array of 18 cell property, with a format of + for each entry, + , indicating the safe luts on sspp and wb. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-creq-lut: + description: | + This u64 array of 18 cell property, with a format of + for each + entry, for qos cases from , with of-node count based + on the qos refresh rates count. + $ref: /schemas/types.yaml#/definitions/uint64-array + + qcom,sde-cdp-setting: + description: | + Array of 2 cell property, with a format of + for cdp use cases in + order of , and . + + qcom,sde-qos-cpu-mask: + description: A u32 value indicating desired PM QoS CPU affine mask. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qos-cpu-mask-performance: + description: | + Each bit represents a CPU mask. For example + 0xf represents 4 cpu cores. These cores can be + silver or gold or gold+. + + qcom,sde-qos-cpu-dma-latency: + description: A u32 value indicating desired PM QoS CPU DMA latency in usec. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qos-cpu-irq-latency: + description: A u32 value indicating desired PM QoS CPU irq latency in usec. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ipcc-protocol-id: + description: A u32 value indicating ipcc protocol id used for hw fencing feature. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ipcc-client-dpu-phys-id: + description: | + A u32 value indicating ipcc physical client id of dpu used + for ipcc registers access. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-inline-rot-xin: + description: An integer array of xin-ids related to inline rotation. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-inline-rot-xin-type: + description: | + A string array indicating the type of xin, + namely sspp or wb. Number of entries should match + the number of xin-ids defined in + property: qcom,sde-inline-rot-xin + $ref: /schemas/types.yaml#/definitions/string-array + enum: [sspp, wb] + + qcom,sde-inline-rot-clk-ctrl: + description: | + Array of offsets describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of xin-ids defined in + property: qcom,sde-inline-rot-xin + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-secure-sid-mask: + description: Array of secure SID masks used during secure-camera/secure-display usecases. + $ref: /schemas/types.yaml#/definitions/uint32-array + + '#power-domain-cells': + description: Number of cells in a power-domain specifier and should contain 0. + + '#list-cells': + description: Number of mdp cells, must be 1. + + qcom,sde-mixer-display-pref: + description: | + A string array indicating the preferred display type + for the mixer block. Possible values: + "primary" - preferred for primary display + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [primary, none] + + qcom,sde-mixer-cwb-pref: + description: | + A string array indicating the preferred mixer block. + for CWB. Possible values: + "cwb" - preferred for cwb + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [cwb, none] + + qcom,sde-mixer-dcwb-pref: + description: | + A string array indicating the preferred mixer block. + for Dedicated-CWB. Possible values: + "dcwb" - preferred for dedicated-cwb + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dcwb, none] + + qcom,sde-ctl-display-pref: + description: | + A string array indicating the preferred display type + for the ctl block. Possible values: + "primary" - preferred for primary display + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [primary, none] + + qcom,sde-pipe-order-version: + description: | + A u32 property to indicate version of pipe + ordering block + 0: lower priority pipe has to be on the left for a given pair of pipes. + 1: priority have to be explicitly configured for a given pair of pipes. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,sde-trusted-vm-env: + description: | + Boolean property to indicate if the device + driver is executing in a trusted VM + + qcom,sde-max-trusted-vm-displays: + description: | + A u32 property to indicate the maximum + number of concurrent displays supported in the + trusted vm environment + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vm-exclude-reg-names: + description: | + A string array indicating the reg-names which + should be excluded from IO memory validation list + in trusted vm environment + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,tvm-include-reg: + description: | + An array of u32 tuplets indicating the address + ranges of the display sub-device registers + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,vram-size: + description: A u32 value indicating the size of the VRAM in bytes + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,pmic-arb-address: + description: | + A u32 array of display related SPMI address + bit mask, which is a combination of SID and pheripheral id's. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-ib-bw-vote: + description: | + A u32 array of IB bandwidth vote values in kbps for + MNOC, LLCC and DDR/EBI respectively. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-version: + description: A u32 value indicating the downscale blur version + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dnsc-blur-off: + description: | + An array of u32 values with the offset for the downscale blur + block, from the "mdp_phys". + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-size: + description: A u32 value indicates the downscale blur block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dnsc-blur-gaus-lut-off: + description: | + An array of u32 values with the offset for gaussian LUT + block, from the dnsc-blur-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-gaus-lut-size: + description: A u32 value indicates the gaussian LUT block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dnsc-blur-dither-off: + description: | + An array of u32 values with the offset for dither + block, from the dnsc-blur-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-dither-size: + description: A u32 value indicates the dither block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + +Bus Scaling: + interconnects: + description: | + An array of 4 cell properties with the format of + (src-noc master-id dst-noc slave-id) as described in: + Documentation/devicetree/bindings/interconnect/interconnect.txt + One entry for each interconnect path available. + Master/Slave ID bindings can be found at: + include/dt-bindings/interconnect/ + $ref: /schemas/types.yaml#/definitions/uint32-array + + interconnect-names: + description: | + An array of string properties associated with "interconnects" + each with a unique name used to lookup the respective path. + The following paths are currently supported: qcom,sde-reg-bus, + qcom,sde-data-bus0, qcom,sde-data-bus1, qcom,sde-llcc-bus, + qcom,sde-ebi-bus + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-reg-bus,vectors-KBps: + description: | + A series of 2 cell properties with a format of + (ab, ib) specified in kilobytes-per-second. + Used when applying reg-bus votes and must be + given whenever "qcom,sde-reg-bus" is used. + + qcom,sde-inline-rotator: + description: | + A 2 cell property, with format of (rotator phandle, + instance id), of inline rotator device. + +patternProperties: + "qcom,smmu_sde_+\w": + description: Child nodes representing sde smmu virtual devices + $ref: /schemas/types.yaml#/definitions/string-array + compatible: + enum: + - qcom,smmu_sde_unsec: + description: smmu context bank device for unsecure sde real time domain. + - qcom,smmu_sde_sec: + description: smmu context bank device for secure sde real time domain. + - qcom,smmu_sde_nrt_unsec: + description: smmu context bank device for unsecure sde non-real time domain. + - qcom,smmu_sde_nrt_sec: + description: smmu context bank device for secure sde non-real time domain. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mmagic-supply + - vdd-supply + - interrupt-parent + - interrupts + - interrupt-controller + - '#interrupt-cells' + - iommus + - qcom,sde-sspp-type + - qcom,sde-sspp-off + - qcom,sde-sspp-xin-id + - qcom,sde-ctl-off + - qcom,sde-wb-off + - qcom,sde-wb-xin-id + - qcom,sde-mixer-off + - qcom,sde-dspp-top-off + - qcom,sde-dspp-off + - qcom,sde-pp-off + - qcom,sde-pp-slave + - qcom,sde-pp-merge-3d-id + - qcom,sde-merge-3d-off + - qcom,sde-intf-off + - qcom,sde-mixer-blend-op-off + - qcom,sde-mixer-pair-mask + +examples: + - | + mdss_mdp: qcom,mdss_mdp@900000 { + compatible = "qcom,sde-kms"; + reg = <0x00900000 0x90000>, + <0x009b0000 0x1040>, + <0x009b8000 0x1040>, + <0x0aeac000 0x00f0>; + reg-names = "mdp_phys", + "vbif_phys", + "vbif_nrt_phys", + "regdma_phys"; + qcom,tvm-include-reg = <0xaf20000 0x4d68>, + <0xaf30000 0x3fd4>; + clocks = <&clock_mmss clk_mdss_ahb_clk>, + <&clock_mmss clk_mdss_axi_clk>, + <&clock_mmss clk_mdp_clk_src>, + <&clock_mmss clk_mdss_mdp_vote_clk>, + <&clock_mmss clk_smmu_mdp_axi_clk>, + <&clock_mmss clk_mmagic_mdss_axi_clk>, + <&clock_mmss clk_mdss_vsync_clk>; + clock-names = "iface_clk", + "bus_clk", + "core_clk_src", + "core_clk", + "iommu_clk", + "mmagic_clk", + "vsync_clk"; + clock-rate = <0>, <0>, <0>; + clock-max-rate= <0 320000000 0>; + qcom,hw-fence-sw-version = <0x1>; + clock-mmrm = <0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0 0 0>; + mmagic-supply = <&gdsc_mmagic_mdss>; + vdd-supply = <&gdsc_mdss>; + interrupt-parent = <&intc>; + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&mdp_smmu 0>; + #power-domain-cells = <0>; + + qcom,sde-hw-version = <0x70000000>; + qcom,sde-emulated-env; + qcom,sde-off = <0x1000>; + qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 + 0x00002600 0x00002800>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + qcom,sde-mixer-off = <0x00045000 0x00046000 + 0x00047000 0x0004a000>; + qcom,sde-mixer-display-pref = "primary", "none", + "none", "none"; + qcom,sde-mixer-cwb-pref = "none", "none", + "cwb", "none"; + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-off = <0x00055000 0x00057000>; + qcom,sde-dspp-ad-off = <0x24000 0x22800>; + qcom,sde-dspp-ad-version = <0x00030000>; + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800 0x14c00>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-min-region-width = <20>; + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>; + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>; + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>; + qcom,sde-dspp-aiqe-version = <0x00010000>; + qcom,sde-dspp-aiqe-size = <0x3fc>; + + qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>; + qcom,sde-dspp-aiqe-dither-version = <0x00010000>; + qcom,sde-dspp-aiqe-dither-size = <0x20>; + + qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>; + qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>; + qcom,sde-dspp-aiqe-wrapper-size = <0x1c>; + + qcom,sde-aiqe-has-feature-mdnie; + qcom,sde-aiqe-has-feature-abc; + qcom,sde-aiqe-has-feature-ssrc; + qcom,sde-aiqe-has-feature-copr; + + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-wb-off = <0x00066000>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-intf-off = <0x0006b000 0x0006b800 + 0x0006c000 0x0006c800>; + qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + qcom,sde-pp-off = <0x00071000 0x00071800 + 0x00072000 0x00072800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; + qcom,sde-cdm-off = <0x0007a200>; + qcom,sde-dsc-off = <0x00081000 0x00081400>; + qcom,sde-vdc-off = <0x7C000>; + qcom,sde-vdc-size = <0xf10>; + qcom,sde-vdc-hw-rev = "vdc_1_2"; + qcom,sde-vdc-enc = <0x200>; + qcom,sde-vdc-ctl = <0xf00>; + qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; + + qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>; + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-qdss-off = <0x81a00>; + + qcom,sde-sspp-type = "vig", "vig", "vig", + "vig", "rgb", "rgb", + "rgb", "rgb", "dma", + "dma", "cursor", "cursor"; + + qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000 + 0x0000b000 0x00015000 0x00017000 + 0x00019000 0x0001b000 0x00025000 + 0x00027000 0x00035000 0x00037000>; + + qcom,sde-sspp-xin-id = <0 4 8 + 12 1 5 + 9 13 2 + 10 7 7>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, + <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, + <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, + <0x3b0 16>; + qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, + <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, + <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, + <0x3b0 16>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2560>; + qcom,sde-mixer-blendstages = <0x7>; + qcom,sde-dsc-linewidth = <2048>; + qcom,sde-highest-bank-bit = <0x7 0x2>; + qcom,sde-ubwc-version = <0x10000000>; + qcom,sde-ubwc-static = <0x100>; + qcom,sde-ubwc-swizzle = <0>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-smart-panel-align-mode = <0xd>; + qcom,sde-panic-per-pipe; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-sspp-src-size = <0x100>; + qcom,sde-mixer-size = <0x100>; + qcom,sde-ctl-size = <0x100>; + qcom,sde-dspp-top-size = <0xc>; + qcom,sde-dspp-size = <0x100>; + qcom,sde-intf-size = <0x100>; + qcom,sde-dsc-size = <0x100>; + qcom,sde-cdm-size = <0x100>; + qcom,sde-pp-size = <0x100>; + qcom,sde-wb-size = <0x100>; + qcom,sde-dest-scaler-top-size = <0xc>; + qcom,sde-dest-scaler-size = <0x800>; + qcom,sde-len = <0x100>; + qcom,sde-wb-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <5120>; + qcom,sde-sspp-scale-size = <0x100>; + qcom,sde-mixer-blendstages = <0x8>; + qcom,sde-qseed-sw-lib-rev = "qseedv2"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-highest-bank-bit = <15>; + qcom,sde-has-mixer-gc; + qcom,sde-has-idle-pc; + qcom,sde-wakeup-with-touch; + qcom,fullsize-va-map; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-sspp-max-rects = <1 1 1 1 + 1 1 1 1 + 1 1 + 1 1>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1 + 1 1 + 1 1>; + qcom,sde-sspp-smart-dma-priority = <0 0 0 0 + 0 0 0 0 + 0 0 + 1 2>; + qcom,sde-smart-dma-rev = "smart_dma_v2"; + qcom,sde-te-off = <0x100>; + qcom,sde-te2-off = <0x100>; + qcom,sde-te-size = <0xffff>; + qcom,sde-te2-size = <0xffff>; + qcom,sde-trusted-vm-env; + + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-qos-refresh-rates = <60 120>; + qcom,sde-danger-lut = <0x3ffff 0x3ffff 0x0 0x0 0x0 0x3fffff 0x3fffff>, + <0x3ffffff 0x3ffffff 0x0 0x0 0x0 0x3ffffff 0x3fffff, + 0xffff0000 0xffff0000>; + qcom,sde-safe-lut = <0xFE00 0xFE00 0xFFFF 0x01 0x03FF 0xF800 0xF800>, + <0xE000 0xE000 0xFFFF 0x01 0x03FF 0xE000 0xF800, 0xff, + 0xff>; + qcom,sde-creq-lut = <0x00112234 0x45566777 0x00112236 0x67777777 + 0x00112234 0x45566777 0x00112236 0x67777777 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x00000000 0x77776541 0x00000000 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x55555544 0x33221100 0x55555544 0x33221100>, + <0x02344455 0x56667777 0x02366677 0x77777777 + 0x02344455 0x56667777 0x02366677 0x77777777 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x00000000 0x77776541 0x00000000 + 0x02344455 0x56667777 0x02366677 0x77777777 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x2>; + qcom,sde-ipcc-client-dpu-phys-id = <0x19>; + + qcom,sde-vbif-off = <0 0>; + qcom,sde-vbif-id = <0 1>; + qcom,sde-vbif-default-ot-rd-limit = <32>; + qcom,sde-vbif-default-ot-wr-limit = <16>; + qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <1>; + + qcom,sde-max-bw-high-kbps = <9000000>; + qcom,sde-max-bw-low-kbps = <9000000>; + + qcom,sde-core-ib-ff = "1.1"; + qcom,sde-core-clk-ff = "1.0"; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; + qcom,sde-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; + qcom,sde-undersized-prefill-lines = <4>; + qcom,sde-xtra-prefill-lines = <5>; + qcom,sde-dest-scale-prefill-lines = <6>; + qcom,sde-macrotile-prefill-lines = <7>; + qcom,sde-yuv-nv12-prefill-lines = <8>; + qcom,sde-linear-prefill-lines = <9>; + qcom,sde-downscaling-prefill-lines = <10>; + qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000 + 2400000 2400000 2400000 2400000>; + qcom,sde-amortizable-threshold = <11>; + qcom,sde-secure-sid-mask = <0x200801 0x200c01>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,vram-size = <0x200000>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; + + qcom,sde-ib-bw-vote = <2500000 0 800000>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6 3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3 3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4 3 3 3 3 4 4 4 4>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-broadcast-disabled = <0>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0xa00>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + /* Offset from vig top, version of HSIC */ + qcom,sde-vig-hsic = <0x200 0x00010000>; + qcom,sde-vig-memcolor = <0x200 0x00010000>; + qcom,sde-vig-pcc = <0x1780 0x00010000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010000>; + qcom,sde-ucsc-unmult = <0x700 0x00010000>; + qcom,sde-ucsc-gc = <0x700 0x00010000>; + qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010000>; + qcom,sde-ucsc-unmult = <0x1700 0x00010000>; + qcom,sde-ucsc-gc = <0x1700 0x00010000>; + qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x800>; + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010000>; + qcom,sde-ucsc-unmult = <0x700 0x00010000>; + qcom,sde-ucsc-gc = <0x700 0x00010000>; + qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010000>; + qcom,sde-ucsc-unmult = <0x1700 0x00010000>; + qcom,sde-ucsc-gc = <0x1700 0x00010000>; + qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-rgb-blocks { + qcom,sde-rgb-scaler-off = <0x200>; + qcom,sde-rgb-scaler-size = <0x74>; + qcom,sde-rgb-pcc = <0x380 0x00010000>; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00010000>; + qcom,sde-dspp-pcc = <0x1700 0x00010000>; + qcom,sde-dspp-gc = <0x17c0 0x00010000>; + qcom,sde-dspp-hsic = <0x0 0x00010000>; + qcom,sde-dspp-memcolor = <0x0 0x00010000>; + qcom,sde-dspp-sixzone = <0x0 0x00010000>; + qcom,sde-dspp-gamut = <0x1600 0x00010000>; + qcom,sde-dspp-dither = <0x0 0x00010000>; + qcom,sde-dspp-hist = <0x0 0x00010000>; + qcom,sde-dspp-vlut = <0x0 0x00010000>; + }; + + qcom,sde-mixer-blocks { + qcom,sde-mixer-gc = <0x3c0 0x00010000>; + }; + + qcom,msm-hdmi-audio-rx { + compatible = "qcom,msm-hdmi-audio-codec-rx"; + }; + + qcom,sde-inline-rotator = <&mdss_rotator 0>; + qcom,sde-inline-rot-xin = <10 11>; + qcom,sde-inline-rot-xin-type = "sspp", "wb"; + qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + + interconnects = <&mmss_noc MASTER_MDP0 &mmss_noc SLAVE_MNOC_HF_MEM_NOC> + <&mmss_noc MASTER_MDP1 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>, + <&gem_noc MASTER_MNOC_HF_MEM_NOC &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-llcc-bus", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + smmu_kms_unsec: qcom,smmu_kms_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&mmss_smmu 0>; + }; + + smmu_kms_sec: qcom,smmu_kms_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&mmss_smmu 1>; + }; + }; +...