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Merge "ARM: dts: qcom: Enable UFS MCQ on Tuna platforms"

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QCTECMDR Service
2024-11-29 05:25:48 -08:00
committed by Gerrit - the friendly Code Review server
parent 3b66c13343 3a9122b108
commit 773a25f282
1 changed files with 11 additions and 3 deletions
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14
qcom/tuna.dtsi
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@@ -2415,8 +2415,10 @@
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>,
<0x1d88000 0x18000>;
reg-names = "ufs_mem", "ice";
<0x1d88000 0x18000>,
<0x1da5000 0x2000>,
<0x1da4000 0x10>;
reg-names = "ufs_mem", "ice", "mcq_sqd", "mcq_vs";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
@@ -2424,6 +2426,9 @@
#reset-cells = <1>;
qcom,ice-use-hwkm;
qcom,prime-mask = <0x80>;
qcom,silver-mask = <0x0f>;
qcom,esi-affinity-mask = <1 1 4 4 3 6 6 7>;
lanes-per-direction = <2>;
clock-names =
@@ -2465,7 +2470,8 @@
depends-on-supply = <&apps_smmu>;
iommus = <&apps_smmu 0x60 0x0>;
qcom,iommu-dma = "bypass";
qcom,iommu-dma = "fastmap";
qcom,iommu-msi-size = <0x1000>;
memory-region = <&ufshc_dma_resv>;
shared-ice-cfg = <&ice_cfg>;
dma-coherent;
@@ -2473,6 +2479,8 @@
qcom,bypass-pbl-rst-wa;
qcom,max-cpus = <8>;
msi-parent = <&gic_its 0x60>;
reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";