Merge "ARM: dts: qcom: Enable UFS MCQ on Tuna platforms"
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@@ -2415,8 +2415,10 @@
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ufshc_mem: ufshc@1d84000 {
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ufshc_mem: ufshc@1d84000 {
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compatible = "qcom,ufshc";
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compatible = "qcom,ufshc";
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reg = <0x1d84000 0x3000>,
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reg = <0x1d84000 0x3000>,
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<0x1d88000 0x18000>;
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<0x1d88000 0x18000>,
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reg-names = "ufs_mem", "ice";
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<0x1da5000 0x2000>,
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<0x1da4000 0x10>;
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reg-names = "ufs_mem", "ice", "mcq_sqd", "mcq_vs";
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufsphy_mem>;
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phys = <&ufsphy_mem>;
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@@ -2424,6 +2426,9 @@
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#reset-cells = <1>;
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#reset-cells = <1>;
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qcom,ice-use-hwkm;
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qcom,ice-use-hwkm;
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qcom,prime-mask = <0x80>;
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qcom,silver-mask = <0x0f>;
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qcom,esi-affinity-mask = <1 1 4 4 3 6 6 7>;
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lanes-per-direction = <2>;
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lanes-per-direction = <2>;
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clock-names =
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clock-names =
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@@ -2465,7 +2470,8 @@
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depends-on-supply = <&apps_smmu>;
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depends-on-supply = <&apps_smmu>;
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iommus = <&apps_smmu 0x60 0x0>;
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iommus = <&apps_smmu 0x60 0x0>;
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qcom,iommu-dma = "bypass";
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qcom,iommu-dma = "fastmap";
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qcom,iommu-msi-size = <0x1000>;
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memory-region = <&ufshc_dma_resv>;
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memory-region = <&ufshc_dma_resv>;
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shared-ice-cfg = <&ice_cfg>;
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shared-ice-cfg = <&ice_cfg>;
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dma-coherent;
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dma-coherent;
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@@ -2473,6 +2479,8 @@
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qcom,bypass-pbl-rst-wa;
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qcom,bypass-pbl-rst-wa;
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qcom,max-cpus = <8>;
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qcom,max-cpus = <8>;
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msi-parent = <&gic_its 0x60>;
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reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
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reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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reset-names = "rst";
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