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Merge "ARM: dts: msm: Update Reference Clock to clk8_a4 for Kera UFS 2.x"

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QCTECMDR Service
2025-01-15 21:51:26 -08:00
committed by Gerrit - the friendly Code Review server
parent c5e6726dbe 67fdf207c7
commit 770aaa1d9b
1 changed files with 32 additions and 1 deletions
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33
qcom/kera_ufs2.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-kera.h>
#include <dt-bindings/clock/qcom,rpmh.h>
@@ -57,5 +57,36 @@
qcom,vccq2-parent-supply = <&S1B>;
qcom,vccq2-parent-max-microamp = <210000>;
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&clk8_a4>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<100000000 403000000>,
<0 0>,
<0 0>,
<100000000 403000000>,
<100000000 403000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
status = "ok";
};