From 73c1325edde09c49ed5c11ecce2b8d53720741d0 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Fri, 11 Aug 2023 02:53:19 -0700 Subject: [PATCH] ARM: dts: msm: Add QUPv3 and GPI DT nodes on SUN Add QUPv3(I2C, SPI, UART and I3C) and GPI DT nodes on SUN. Change-Id: I2520da18d152eb0a30a9f735d879422e876d2d6a Signed-off-by: Chandana Kishori Chiluveru --- qcom/sun-pinctrl.dtsi | 2630 +++++++++++++++++++++++++++++++++++++++++ qcom/sun-qupv3.dtsi | 1256 +++++++++++++++++++- qcom/sun.dtsi | 1 + 3 files changed, 3882 insertions(+), 5 deletions(-) diff --git a/qcom/sun-pinctrl.dtsi b/qcom/sun-pinctrl.dtsi index a86e4c39..6bfde5c7 100644 --- a/qcom/sun-pinctrl.dtsi +++ b/qcom/sun-pinctrl.dtsi @@ -476,4 +476,2634 @@ }; }; }; + + qupv3_se14_4uart_pins: qupv3_se14_4uart_pins { + qupv3_se14_default_cts: qupv3_se14_default_cts { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_default_rts: qupv3_se14_default_rts { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se14_default_tx: qupv3_se14_default_tx { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_default_rx: qupv3_se14_default_rx { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se14_cts: qupv3_se14_cts { + mux { + pins = "gpio24"; + function = "qup2_se6_l0"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_rts: qupv3_se14_rts { + mux { + pins = "gpio25"; + function = "qup2_se6_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se14_tx: qupv3_se14_tx { + mux { + pins = "gpio26"; + function = "qup2_se6_l2"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_rx_active: qupv3_se14_rx_active { + mux { + pins = "gpio27"; + function = "qup2_se6_l3"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* RX to be in gpio mode for sleep config */ + qupv3_se14_rx_wake: qupv3_se14_rx_wake { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio32"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio32"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio33"; + function = "qup1_se0_l1 "; + }; + + config { + pins = "gpio33"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se0_i3c_pins: qupv3_se0_i3c_pins { + qupv3_se0_i3c_sda_active: qupv3_se0_i3c_sda_active { + mux { + pins = "gpio32"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio32"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se0_i3c_scl_active: qupv3_se0_i3c_scl_active { + mux { + pins = "gpio33"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio33"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se0_i3c_sda_sleep: qupv3_se0_i3c_sda_sleep { + mux { + pins = "gpio32"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio32"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se0_i3c_scl_sleep: qupv3_se0_i3c_scl_sleep { + mux { + pins = "gpio33"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio33"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se0_i3c_disable: qupv3_se0_i3c_disable { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { + mux { + pins = "gpio32"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio32"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { + mux { + pins = "gpio33"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { + mux { + pins = "gpio34"; + function = "qup1_se0_l2"; + }; + + config { + pins = "gpio34"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { + mux { + pins = "gpio35"; + function = "qup1_se0_l3"; + }; + + config { + pins = "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { + mux { + pins = "gpio36"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active { + mux { + pins = "gpio37"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active { + mux { + pins = "gpio36"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio36"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active { + mux { + pins = "gpio37"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio37"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active { + mux { + pins = "gpio38"; + function = "qup1_se1_l2"; + }; + + config { + pins = "gpio38"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active { + mux { + pins = "gpio39"; + function = "qup1_se1_l3"; + }; + + config { + pins = "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_i3c_pins: qupv3_se1_i3c_pins { + qupv3_se1_i3c_sda_active: qupv3_se1_i3c_sda_active { + mux { + pins = "gpio36"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio36"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se1_i3c_scl_active: qupv3_se1_i3c_scl_active { + mux { + pins = "gpio37"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio37"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se1_i3c_sda_sleep: qupv3_se1_i3c_sda_sleep { + mux { + pins = "gpio36"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio36"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se1_i3c_scl_sleep: qupv3_se1_i3c_scl_sleep { + mux { + pins = "gpio37"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio37"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se1_i3c_disable: qupv3_se1_i3c_disable { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { + mux { + pins = "gpio40"; + function = "qup1_se2_l0"; + }; + + config { + pins = "gpio40"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { + mux { + pins = "gpio41"; + function = "qup1_se2_l1"; + }; + + config { + pins = "gpio41"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio40", "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { + mux { + pins = "gpio40"; + function = "qup1_se2_l0"; + }; + + config { + pins = "gpio40"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { + mux { + pins = "gpio41"; + function = "qup1_se2_l1"; + }; + + config { + pins = "gpio41"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { + mux { + pins = "gpio42"; + function = "qup1_se2_l2"; + }; + + config { + pins = "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { + mux { + pins = "gpio43"; + function = "qup1_se2_l3"; + }; + + config { + pins = "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { + mux { + pins = "gpio44"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio45"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { + mux { + pins = "gpio44"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio44"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { + mux { + pins = "gpio45"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio45"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { + mux { + pins = "gpio46"; + function = "qup1_se3_l2"; + }; + + config { + pins = "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { + mux { + pins = "gpio47"; + function = "qup1_se3_l3"; + }; + + config { + pins = "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { + mux { + pins = "gpio48"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { + mux { + pins = "gpio49"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio49"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio48", "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se4_i3c_pins: qupv3_se4_i3c_pins { + qupv3_se4_i3c_sda_active: qupv3_se4_i3c_sda_active { + mux { + pins = "gpio48"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio48"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se4_i3c_scl_active: qupv3_se4_i3c_scl_active { + mux { + pins = "gpio49"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio49"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se4_i3c_sda_sleep: qupv3_se4_i3c_sda_sleep { + mux { + pins = "gpio48"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio48"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se4_i3c_scl_sleep: qupv3_se4_i3c_scl_sleep { + mux { + pins = "gpio49"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio49"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se4_i3c_disable: qupv3_se4_i3c_disable { + mux { + pins = "gpio48", "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active { + mux { + pins = "gpio48"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio48"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active { + mux { + pins = "gpio49"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio49"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active { + mux { + pins = "gpio50"; + function = "qup1_se4_l2"; + }; + + config { + pins = "gpio50"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active { + mux { + pins = "gpio51"; + function = "qup1_se4_l3"; + }; + + config { + pins = "gpio51"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { + mux { + pins = "gpio52"; + function = "qup1_se5_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio53"; + function = "qup1_se5_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active { + mux { + pins = "gpio52"; + function = "qup1_se5_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active { + mux { + pins = "gpio53"; + function = "qup1_se5_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active { + mux { + pins = "gpio54"; + function = "qup1_se5_l2"; + }; + + config { + pins = "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active { + mux { + pins = "gpio55"; + function = "qup1_se5_l3"; + }; + + config { + pins = "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio56"; + function = "qup1_se6_l0"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio57"; + function = "qup1_se6_l1"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio56"; + function = "qup1_se6_l0"; + }; + + config { + pins = "gpio56"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio57"; + function = "qup1_se6_l1"; + }; + + config { + pins = "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio58"; + function = "qup1_se6_l2"; + }; + + config { + pins = "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio59"; + function = "qup1_se6_l3"; + }; + + config { + pins = "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active { + mux { + pins = "gpio0"; + function = "qup2_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active { + mux { + pins = "gpio1"; + function = "qup2_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active { + mux { + pins = "gpio0"; + function = "qup2_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active { + mux { + pins = "gpio1"; + function = "qup2_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active { + mux { + pins = "gpio2"; + function = "qup2_se0_l2"; + }; + + config { + pins = "gpio2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active { + mux { + pins = "gpio3"; + function = "qup2_se0_l3"; + }; + + config { + pins = "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_i3c_pins: qupv3_se8_i3c_pins { + qupv3_se8_i3c_sda_active: qupv3_se8_i3c_sda_active { + mux { + pins = "gpio0"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio0"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se8_i3c_scl_active: qupv3_se8_i3c_scl_active { + mux { + pins = "gpio1"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio1"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se8_i3c_sda_sleep: qupv3_se8_i3c_sda_sleep { + mux { + pins = "gpio0"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio0"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se8_i3c_scl_sleep: qupv3_se8_i3c_scl_sleep { + mux { + pins = "gpio1"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio1"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se8_i3c_disable: qupv3_se8_i3c_disable { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active { + mux { + pins = "gpio4"; + function = "qup2_se1_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active { + mux { + pins = "gpio5"; + function = "qup2_se1_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_miso_active: qupv3_se9_spi_miso_active { + mux { + pins = "gpio4"; + function = "qup2_se1_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_mosi_active: qupv3_se9_spi_mosi_active { + mux { + pins = "gpio5"; + function = "qup2_se1_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_clk_active: qupv3_se9_spi_clk_active { + mux { + pins = "gpio6"; + function = "qup2_se1_l2"; + }; + + config { + pins = "gpio6"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_cs_active: qupv3_se9_spi_cs_active { + mux { + pins = "gpio7"; + function = "qup2_se1_l3"; + }; + + config { + pins = "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_i3c_pins: qupv3_se9_i3c_pins { + qupv3_se9_i3c_sda_active: qupv3_se9_i3c_sda_active { + mux { + pins = "gpio4"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio4"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se9_i3c_scl_active: qupv3_se9_i3c_scl_active { + mux { + pins = "gpio5"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio5"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se9_i3c_sda_sleep: qupv3_se9_i3c_sda_sleep { + mux { + pins = "gpio4"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio4"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se9_i3c_scl_sleep: qupv3_se9_i3c_scl_sleep { + mux { + pins = "gpio5"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio5"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se9_i3c_disable: qupv3_se9_i3c_disable { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_sda_active: qupv3_se10_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup2_se2_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se10_i2c_scl_active: qupv3_se10_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup2_se2_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_miso_active: qupv3_se10_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup2_se2_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_mosi_active: qupv3_se10_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup2_se2_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_clk_active: qupv3_se10_spi_clk_active { + mux { + pins = "gpio10"; + function = "qup2_se2_l2"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_cs_active: qupv3_se10_spi_cs_active { + mux { + pins = "gpio11"; + function = "qup2_se2_l3"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_i3c_pins: qupv3_se10_i3c_pins { + qupv3_se10_i3c_sda_active: qupv3_se10_i3c_sda_active { + mux { + pins = "gpio8"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio8"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se10_i3c_scl_active: qupv3_se10_i3c_scl_active { + mux { + pins = "gpio9"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio9"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se10_i3c_sda_sleep: qupv3_se10_i3c_sda_sleep { + mux { + pins = "gpio8"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio8"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se10_i3c_scl_sleep: qupv3_se10_i3c_scl_sleep { + mux { + pins = "gpio9"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio9"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se10_i3c_disable: qupv3_se10_i3c_disable { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_sda_active: qupv3_se11_i2c_sda_active { + mux { + pins = "gpio12"; + function = "qup2_se3_l0"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se11_i2c_scl_active: qupv3_se11_i2c_scl_active { + mux { + pins = "gpio13"; + function = "qup2_se3_l1"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_miso_active: qupv3_se11_spi_miso_active { + mux { + pins = "gpio12"; + function = "qup2_se3_l0"; + }; + + config { + pins = "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_mosi_active: qupv3_se11_spi_mosi_active { + mux { + pins = "gpio13"; + function = "qup2_se3_l1"; + }; + + config { + pins = "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_clk_active: qupv3_se11_spi_clk_active { + mux { + pins = "gpio14"; + function = "qup2_se2_l2"; + }; + + config { + pins = "gpio14"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_cs_active: qupv3_se11_spi_cs_active { + mux { + pins = "gpio15"; + function = "qup2_se3_l3"; + }; + + config { + pins = "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_i3c_pins: qupv3_se11_i3c_pins { + qupv3_se11_i3c_sda_active: qupv3_se11_i3c_sda_active { + mux { + pins = "gpio12"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio12"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se11_i3c_scl_active: qupv3_se11_i3c_scl_active { + mux { + pins = "gpio13"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio13"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se11_i3c_sda_sleep: qupv3_se11_i3c_sda_sleep { + mux { + pins = "gpio12"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio12"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se11_i3c_scl_sleep: qupv3_se11_i3c_scl_sleep { + mux { + pins = "gpio13"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio13"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se11_i3c_disable: qupv3_se11_i3c_disable { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_sda_active: qupv3_se12_i2c_sda_active { + mux { + pins = "gpio16"; + function = "qup2_se4_l0"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se12_i2c_scl_active: qupv3_se12_i2c_scl_active { + mux { + pins = "gpio17"; + function = "qup2_se4_l1"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_miso_active: qupv3_se12_spi_miso_active { + mux { + pins = "gpio16"; + function = "qup2_se4_l0"; + }; + + config { + pins = "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_mosi_active: qupv3_se12_spi_mosi_active { + mux { + pins = "gpio17"; + function = "qup2_se4_l1"; + }; + + config { + pins = "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_clk_active: qupv3_se12_spi_clk_active { + mux { + pins = "gpio18"; + function = "qup2_se4_l2"; + }; + + config { + pins = "gpio18"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_cs_active: qupv3_se12_spi_cs_active { + mux { + pins = "gpio19"; + function = "qup2_se4_l3"; + }; + + config { + pins = "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_sda_active: qupv3_se13_i2c_sda_active { + mux { + pins = "gpio20"; + function = "qup2_se5_l0"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se13_i2c_scl_active: qupv3_se13_i2c_scl_active { + mux { + pins = "gpio21"; + function = "qup2_se5_l1"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_miso_active: qupv3_se13_spi_miso_active { + mux { + pins = "gpio20"; + function = "qup2_se5_l0"; + }; + + config { + pins = "gpio20"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_mosi_active: qupv3_se13_spi_mosi_active { + mux { + pins = "gpio21"; + function = "qup2_se5_l1"; + }; + + config { + pins = "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_clk_active: qupv3_se13_spi_clk_active { + mux { + pins = "gpio22"; + function = "qup2_se5_l2"; + }; + + config { + pins = "gpio22"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_cs_active: qupv3_se13_spi_cs_active { + mux { + pins = "gpio23"; + function = "qup2_se5_l3"; + }; + + config { + pins = "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_sda_active: qupv3_se15_i2c_sda_active { + mux { + pins = "gpio28"; + function = "qup2_se7_l0"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se15_i2c_scl_active: qupv3_se15_i2c_scl_active { + mux { + pins = "gpio29"; + function = "qup2_se7_l1"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_miso_active: qupv3_se15_spi_miso_active { + mux { + pins = "gpio28"; + function = "qup2_se7_l0"; + }; + + config { + pins = "gpio28"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_mosi_active: qupv3_se15_spi_mosi_active { + mux { + pins = "gpio29"; + function = "qup2_se7_l1"; + }; + + config { + pins = "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_clk_active: qupv3_se15_spi_clk_active { + mux { + pins = "gpio30"; + function = "qup2_se7_l2"; + }; + + config { + pins = "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_cs_active: qupv3_se15_spi_cs_active { + mux { + pins = "gpio31"; + function = "qup2_se7_l3"; + }; + + config { + pins = "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_i3c_pins: qupv3_se15_i3c_pins { + qupv3_se15_i3c_sda_active: qupv3_se15_i3c_sda_active { + mux { + pins = "gpio28"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio28"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se15_i3c_scl_active: qupv3_se15_i3c_scl_active { + mux { + pins = "gpio29"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio29"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se15_i3c_sda_sleep: qupv3_se15_i3c_sda_sleep { + mux { + pins = "gpio28"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio28"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se15_i3c_scl_sleep: qupv3_se15_i3c_scl_sleep { + mux { + pins = "gpio29"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio29"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se15_i3c_disable: qupv3_se15_i3c_disable { + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_hub_i2c0_pins: qupv3_hub_i2c0_pins { + qupv3_hub_i2c0_sda_active: qupv3_hub_i2c0_sda_active { + mux { + pins = "gpio64"; + function = "i2chub0_se0_l0"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c0_scl_active: qupv3_hub_i2c0_scl_active { + mux { + pins = "gpio65"; + function = "i2chub0_se0_l1"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c0_sleep: qupv3_hub_i2c0_sleep { + mux { + pins = "gpio64", "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + }; + }; + }; + + qupv3_hub_i2c1_pins: qupv3_hub_i2c1_pins { + qupv3_hub_i2c1_sda_active: qupv3_hub_i2c1_sda_active { + mux { + pins = "gpio66"; + function = "i2chub0_se1_l0"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c1_scl_active: qupv3_hub_i2c1_scl_active { + mux { + pins = "gpio67"; + function = "i2chub0_se1_l1"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c1_sleep: qupv3_hub_i2c1_sleep { + mux { + pins = "gpio66", "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio66", "gpio67"; + drive-strength = <2>; + }; + }; + }; + + qupv3_hub_i2c2_pins: qupv3_hub_i2c2_pins { + qupv3_hub_i2c2_sda_active: qupv3_hub_i2c2_sda_active { + mux { + pins = "gpio68"; + function = "i2chub0_se2_l0"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c2_scl_active: qupv3_hub_i2c2_scl_active { + mux { + pins = "gpio69"; + function = "i2chub0_se2_l1"; + }; + + config { + pins = "gpio69"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c2_sleep: qupv3_hub_i2c2_sleep { + mux { + pins = "gpio68", "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio68", "gpio69"; + drive-strength = <2>; + }; + }; + }; + + qupv3_hub_i2c3_pins: qupv3_hub_i2c3_pins { + qupv3_hub_i2c3_sda_active: qupv3_hub_i2c3_sda_active { + mux { + pins = "gpio70"; + function = "i2chub0_se3_l0"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c3_scl_active: qupv3_hub_i2c3_scl_active { + mux { + pins = "gpio71"; + function = "i2chub0_se3_l1"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c3_sleep: qupv3_hub_i2c3_sleep { + mux { + pins = "gpio70", "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio70", "gpio71"; + drive-strength = <2>; + }; + }; + }; + + qupv3_hub_i2c4_pins: qupv3_hub_i2c4_pins { + qupv3_hub_i2c4_sda_active: qupv3_hub_i2c4_sda_active { + mux { + pins = "gpio72"; + function = "i2chub0_se4_l0"; + }; + + config { + pins = "gpio72"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c4_scl_active: qupv3_hub_i2c4_scl_active { + mux { + pins = "gpio73"; + function = "i2chub0_se4_l1"; + }; + + config { + pins = "gpio73"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c4_sleep: qupv3_hub_i2c4_sleep { + mux { + pins = "gpio72", "gpio73"; + function = "gpio"; + }; + + config { + pins = "gpio72", "gpio73"; + drive-strength = <2>; + }; + }; + }; + + qupv3_hub_i2c5_pins: qupv3_hub_i2c5_pins { + qupv3_hub_i2c5_sda_active: qupv3_hub_i2c5_sda_active { + mux { + pins = "gpio74"; + function = "i2chub0_se5_l0"; + }; + + config { + pins = "gpio74"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c5_scl_active: qupv3_hub_i2c5_scl_active { + mux { + pins = "gpio75"; + function = "i2chub0_se5_l1"; + }; + + config { + pins = "gpio75"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c5_sleep: qupv3_hub_i2c5_sleep { + mux { + pins = "gpio74", "gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio74", "gpio75"; + drive-strength = <2>; + }; + }; + }; + + qupv3_hub_i2c6_pins: qupv3_hub_i2c6_pins { + qupv3_hub_i2c6_sda_active: qupv3_hub_i2c6_sda_active { + mux { + pins = "gpio76"; + function = "i2chub0_se6_l0"; + }; + + config { + pins = "gpio76"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c6_scl_active: qupv3_hub_i2c6_scl_active { + mux { + pins = "gpio77"; + function = "i2chub0_se6_l1"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c6_sleep: qupv3_hub_i2c6_sleep { + mux { + pins = "gpio76", "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio76", "gpio77"; + drive-strength = <2>; + }; + }; + }; + + qupv3_hub_i2c7_pins: qupv3_hub_i2c7_pins { + qupv3_hub_i2c7_sda_active: qupv3_hub_i2c7_sda_active { + mux { + pins = "gpio82"; + function = "i2chub0_se7_l0"; + }; + + config { + pins = "gpio82"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c7_scl_active: qupv3_hub_i2c7_scl_active { + mux { + pins = "gpio83"; + function = "i2chub0_se7_l1"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c7_sleep: qupv3_hub_i2c7_sleep { + mux { + pins = "gpio82", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + }; + }; + }; + + qupv3_hub_i2c8_pins: qupv3_hub_i2c8_pins { + qupv3_hub_i2c8_sda_active: qupv3_hub_i2c8_sda_active { + mux { + pins = "gpio206"; + function = "i2chub0_se8_l0"; + }; + + config { + pins = "gpio206"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c8_scl_active: qupv3_hub_i2c8_scl_active { + mux { + pins = "gpio207"; + function = "i2chub0_se8_l1"; + }; + + config { + pins = "gpio207"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c8_sleep: qupv3_hub_i2c8_sleep { + mux { + pins = "gpio206", "gpio207"; + function = "gpio"; + }; + + config { + pins = "gpio206", "gpio207"; + drive-strength = <2>; + }; + }; + }; + + qupv3_hub_i2c9_pins: qupv3_hub_i2c9_pins { + qupv3_hub_i2c9_sda_active: qupv3_hub_i2c9_sda_active { + mux { + pins = "gpio80"; + function = "i2chub0_se9_l0"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c9_scl_active: qupv3_hub_i2c9_scl_active { + mux { + pins = "gpio81"; + function = "i2chub0_se9_l1"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c9_sleep: qupv3_hub_i2c9_sleep { + mux { + pins = "gpio80", "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <2>; + }; + }; + }; }; diff --git a/qcom/sun-qupv3.dtsi b/qcom/sun-qupv3.dtsi index 7a81d7c2..2299bd67 100644 --- a/qcom/sun-qupv3.dtsi +++ b/qcom/sun-qupv3.dtsi @@ -4,30 +4,1276 @@ */ &soc { - /* QUPv3_1 Wrapper Instance */ - qupv3_1: qcom,qupv3_1_geni_se@AC0000 { + /* QUPv3 SE Instances + * Qup1 0: SE 0 + * Qup1 1: SE 1 + * Qup1 2: SE 2 + * Qup1 3: SE 3 + * Qup1 4: SE 4 + * Qup1 5: SE 5 + * Qup1 6: SE 6 + * Qup1 7: SE 7 + * Qup2 0: SE 8 + * Qup2 1: SE 9 + * Qup2 2: SE 10 + * Qup2 3: SE 11 + * Qup2 4: SE 12 + * Qup2 5: SE 13 + * Qup2 6: SE 14 + * Qup2 7: SE 15 + */ + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xb6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x1e>; + qcom,ev-factor = <1>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { compatible = "qcom,geni-se-qup"; - reg = <0xAC0000 0x2000>; + reg = <0xac0000 0x2000>; #address-cells = <1>; #size-cells = <1>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xa3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; ranges; status = "ok"; + qupv3_se0_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se0_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, + <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* NFC I3C Instance */ + i3c0: i3c-master@a80000 { + compatible = "qcom,geni-i3c"; + reg = <0xa80000 0x4000>, + <0xec90000 0x10000>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se0_i3c_sda_active>, <&qupv3_se0_i3c_scl_active>; + pinctrl-1 = <&qupv3_se0_i3c_sda_sleep>, <&qupv3_se0_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se0_i3c_disable>; + interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 31 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 30 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <0>; + dmas = <&gpi_dma1 0 0 4 64 0>, + <&gpi_dma1 1 0 4 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, + <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* I3C Instance */ + i3c1: i3c-master@a84000 { + compatible = "qcom,geni-i3c"; + reg = <0xa84000 0x4000>, + <0xeca0000 0x10000>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se1_i3c_sda_active>, <&qupv3_se1_i3c_scl_active>; + pinctrl-1 = <&qupv3_se1_i3c_sda_sleep>, <&qupv3_se1_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se1_i3c_disable>; + interrupts-extended = <&intc GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 33 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 32 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <1>; + dmas = <&gpi_dma1 0 1 4 64 0>, + <&gpi_dma1 1 1 4 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se2_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, + <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>, + <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* Touchscreen I2C Instance */ + qupv3_se4_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma1 0 4 3 64 2>, + <&gpi_dma1 1 4 3 64 2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + /* Touchscreen SPI Instance */ + qupv3_se4_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>, + <&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma1 0 4 1 64 2>, + <&gpi_dma1 1 4 1 64 2>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + i3c2: i3c-master@a90000 { + compatible = "qcom,geni-i3c"; + reg = <0xa90000 0x4000>, + <0xecb0000 0x10000>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se4_i3c_sda_active>, <&qupv3_se4_i3c_scl_active>; + pinctrl-1 = <&qupv3_se4_i3c_sda_sleep>, <&qupv3_se4_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se4_i3c_disable>; + interrupts-extended = <&intc GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 35 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 34 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <2>; + dmas = <&gpi_dma1 0 4 4 64 0>, + <&gpi_dma1 1 4 4 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma1 0 5 3 64 0>, + <&gpi_dma1 1 5 3 64 0>; + dma-names = "tx", "rx"; + qcom,shared; + status = "disabled"; + }; + + qupv3_se5_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>, + <&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma1 0 6 3 64 0>, + <&gpi_dma1 1 6 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@a98000 { + compatible = "qcom,spi-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma1 0 6 1 64 0>, + <&gpi_dma1 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + /* Debug UART Instance */ - qupv3_se7_2uart: qcom,qup_uart@A9C000 { + qupv3_se7_2uart: qcom,qup_uart@a9c000 { compatible = "qcom,geni-debug-uart"; - reg = <0xA9C000 0x4000>; + reg = <0xa9c000 0x4000>; reg-names = "se_phys"; interrupts = ; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>; pinctrl-1 = <&qupv3_se7_2uart_sleep>; status = "disabled"; }; }; + + /* GPI Instance */ + gpi_dma2: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x436 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x1e>; + qcom,ev-factor = <1>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x423 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + qupv3_se8_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma2 0 0 3 64 0>, + <&gpi_dma2 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se8_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>, + <&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + dmas = <&gpi_dma2 0 0 1 64 0>, + <&gpi_dma2 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* Camera I3C Instance */ + i3c3: i3c-master@880000 { + compatible = "qcom,geni-i3c"; + reg = <0x880000 0x4000>, + <0xecd0000 0x10000>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se8_i3c_sda_active>, <&qupv3_se8_i3c_scl_active>; + pinctrl-1 = <&qupv3_se8_i3c_sda_sleep>, <&qupv3_se8_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se8_i3c_disable>; + interrupts-extended = <&intc GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 48 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <3>; + dmas = <&gpi_dma1 0 0 4 1024 0>, + <&gpi_dma1 1 0 4 1024 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + dmas = <&gpi_dma2 0 1 3 64 0>, + <&gpi_dma2 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se9_spi: spi@884000 { + compatible = "qcom,spi-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>, + <&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + dmas = <&gpi_dma2 0 1 1 64 0>, + <&gpi_dma2 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* I3C Instance */ + i3c4: i3c-master@884000 { + compatible = "qcom,geni-i3c"; + reg = <0x884000 0x4000>, + <0xecd0000 0x10000>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se9_i3c_sda_active>, <&qupv3_se9_i3c_scl_active>; + pinctrl-1 = <&qupv3_se9_i3c_sda_sleep>, <&qupv3_se9_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se9_i3c_disable>; + interrupts-extended = <&intc GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 48 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <4>; + dmas = <&gpi_dma1 0 1 4 64 0>, + <&gpi_dma1 1 1 4 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_sda_active>, <&qupv3_se10_i2c_scl_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + dmas = <&gpi_dma2 0 2 3 64 0>, + <&gpi_dma2 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se10_spi: spi@888000 { + compatible = "qcom,spi-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_mosi_active>, <&qupv3_se10_spi_miso_active>, + <&qupv3_se10_spi_clk_active>, <&qupv3_se10_spi_cs_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + dmas = <&gpi_dma2 0 2 1 64 0>, + <&gpi_dma2 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* I3C Instance QUPV3_2, SE2: NAON */ + i3c5: i3c-master@888000 { + compatible = "qcom,geni-i3c"; + reg = <0x888000 0x4000>, + <0xb00000 0x10000>; + clock-names = "se-clk", + "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&gcc GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK>, + <&gcc GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC>; + qcom,ibic-naon; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se10_i3c_sda_active>, <&qupv3_se10_i3c_scl_active>; + pinctrl-1 = <&qupv3_se10_i3c_sda_sleep>, <&qupv3_se10_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se10_i3c_disable>; + interrupts = , + , + ; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <6>; + dmas = <&gpi_dma1 0 2 4 64 0>, + <&gpi_dma1 1 2 4 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_sda_active>, <&qupv3_se11_i2c_scl_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + dmas = <&gpi_dma2 0 3 3 64 0>, + <&gpi_dma2 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se11_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_mosi_active>, <&qupv3_se11_spi_miso_active>, + <&qupv3_se11_spi_clk_active>, <&qupv3_se11_spi_cs_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + dmas = <&gpi_dma2 0 3 1 64 0>, + <&gpi_dma2 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* I3C Instance QUPV3_2, SE3: NAON */ + i3c6: i3c-master@88c000 { + compatible = "qcom,geni-i3c"; + reg = <0x88c000 0x4000>, + <0xb10000 0x10000>; + clock-names = "se-clk", + "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC>; + qcom,ibic-naon; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se11_i3c_sda_active>, <&qupv3_se11_i3c_scl_active>; + pinctrl-1 = <&qupv3_se11_i3c_sda_sleep>, <&qupv3_se11_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se11_i3c_disable>; + interrupts = , + , + ; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <7>; + dmas = <&gpi_dma1 0 3 4 64 0>, + <&gpi_dma1 1 3 4 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_sda_active>, <&qupv3_se12_i2c_scl_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + dmas = <&gpi_dma2 0 4 3 64 0>, + <&gpi_dma2 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se12_spi: spi@890000 { + compatible = "qcom,spi-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_mosi_active>, <&qupv3_se12_spi_miso_active>, + <&qupv3_se12_spi_clk_active>, <&qupv3_se12_spi_cs_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + dmas = <&gpi_dma2 0 4 1 64 0>, + <&gpi_dma2 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_sda_active>, <&qupv3_se13_i2c_scl_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + dmas = <&gpi_dma2 0 5 3 64 0>, + <&gpi_dma2 1 5 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se13_spi: spi@894000 { + compatible = "qcom,spi-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_mosi_active>, <&qupv3_se13_spi_miso_active>, + <&qupv3_se13_spi_clk_active>, <&qupv3_se13_spi_cs_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + dmas = <&gpi_dma2 0 5 1 64 0>, + <&gpi_dma2 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se14_4uart: qcom,qup_uart@898000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x898000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 27 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>, + <&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>; + pinctrl-1 = <&qupv3_se14_cts>, <&qupv3_se14_rts>, + <&qupv3_se14_tx>, <&qupv3_se14_rx_active>; + pinctrl-2 = <&qupv3_se14_cts>, <&qupv3_se14_rts>, + <&qupv3_se14_tx>, <&qupv3_se14_rx_wake>; + pinctrl-3 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>, + <&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + /* Secondary Tounch */ + qupv3_se15_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + dmas = <&gpi_dma2 0 7 3 64 0>, + <&gpi_dma2 1 7 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + /* Secondary Tounch */ + qupv3_se15_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>, + <&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + dmas = <&gpi_dma2 0 7 1 64 0>, + <&gpi_dma2 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* I3C Instance */ + i3c7: i3c-master@89c000 { + compatible = "qcom,geni-i3c"; + reg = <0x89c000 0x4000>, + <0xece0000 0x10000>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se15_i3c_sda_active>, <&qupv3_se15_i3c_scl_active>; + pinctrl-1 = <&qupv3_se15_i3c_sda_sleep>, <&qupv3_se15_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se15_i3c_disable>; + interrupts-extended = <&intc GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 50 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 49 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <4>; + dmas = <&gpi_dma1 0 7 4 64 0>, + <&gpi_dma1 1 7 4 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + /* QUPv3_0 I2C master hub */ + qupv3_0_i2c_hub: qcom,qupv3_i2c_geni_se@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x9c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + /* Upstream common driver using m-ahb and s-ahb clocks, for i2c-hub HW + * supports only s-ahb clock. To support upstream model we are using both + * the clocks, but for m-ahb clock we defined s-ahb clock node only. + */ + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>, + <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + ranges; + status = "ok"; + + qupv3_hub_i2c0: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c0_sda_active>, <&qupv3_hub_i2c0_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c0_sleep>; + qcom,i2c-hub; + status = "disabled"; + }; + + qupv3_hub_i2c1: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c1_sda_active>, <&qupv3_hub_i2c1_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c1_sleep>; + qcom,i2c-hub; + status = "disabled"; + }; + + qupv3_hub_i2c2: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c2_sda_active>, <&qupv3_hub_i2c2_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c2_sleep>; + qcom,i2c-hub; + status = "disabled"; + }; + + qupv3_hub_i2c3: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c3_sda_active>, <&qupv3_hub_i2c3_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c3_sleep>; + qcom,i2c-hub; + status = "disabled"; + }; + + qupv3_hub_i2c4: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c4_sda_active>, <&qupv3_hub_i2c4_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c4_sleep>; + qcom,i2c-hub; + status = "disabled"; + }; + + qupv3_hub_i2c5: i2c@994000 { + compatible = "qcom,i2c-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c5_sda_active>, <&qupv3_hub_i2c5_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c5_sleep>; + qcom,i2c-hub; + status = "disabled"; + }; + + qupv3_hub_i2c6: i2c@998000 { + compatible = "qcom,i2c-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c6_sda_active>, <&qupv3_hub_i2c6_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c6_sleep>; + qcom,i2c-hub; + status = "disabled"; + }; + + qupv3_hub_i2c7: i2c@99c000 { + compatible = "qcom,i2c-geni"; + reg = <0x99c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c7_sda_active>, <&qupv3_hub_i2c7_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c7_sleep>; + qcom,i2c-hub; + status = "disabled"; + }; + + qupv3_hub_i2c8: i2c@9a0000 { + compatible = "qcom,i2c-geni"; + reg = <0x9a0000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c8_sda_active>, <&qupv3_hub_i2c8_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c8_sleep>; + qcom,i2c-hub; + status = "disabled"; + }; + + qupv3_hub_i2c9: i2c@9a4000 { + compatible = "qcom,i2c-geni"; + reg = <0x9a4000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c9_sda_active>, <&qupv3_hub_i2c9_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c9_sleep>; + qcom,i2c-hub; + status = "disabled"; + }; + + }; }; diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 4338045b..7554dd5f 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -39,6 +39,7 @@ aliases: aliases { serial0 = &qupv3_se7_2uart; + hsuart0 = &qupv3_se14_4uart; ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ sdhc2 = &sdhc_2; };