From 72febc66254355fd470dd05c508e58a912b74972 Mon Sep 17 00:00:00 2001
From: Rashid Zafar <quic_rzafar@quicinc.com>
Date: Wed, 8 Nov 2023 13:50:00 -0800
Subject: [PATCH] dt-bindings: soc: qcom: Add pcie-pdc device bindings

Document pcie-pdc device bindings.

Change-Id: Iba3a52dc3ac6c08a6ef7bedc6a0ceece9d59ffc0
Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
---
 bindings/soc/qcom/qcom,pcie-pdc.yaml | 43 ++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 bindings/soc/qcom/qcom,pcie-pdc.yaml

diff --git a/bindings/soc/qcom/qcom,pcie-pdc.yaml b/bindings/soc/qcom/qcom,pcie-pdc.yaml
new file mode 100644
index 00000000..8010730e
--- /dev/null
+++ b/bindings/soc/qcom/qcom,pcie-pdc.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,pcie-pdc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. (QTI) PCIe PDC Device
+
+maintainers:
+  - Maulik Shah <quic_mkshah@quicinc.com>
+  - Rashid Zafar <quic_rzafar@quicinc.com>
+
+description:
+  Support for configuring IRQ at PCIe PDC interrupt controller.
+  GPIO IRQs can be made wake up capable at PCIe PDC to allow SoC exit
+  from deepest low power modes.
+
+properties:
+  compatible:
+    enum:
+      - qcom,sun-pcie-pdc
+      - qcom,pineapple-pcie-pdc
+      - qcom,cliffs-pcie-pdc
+      - qcom,pcie-pdc
+
+  reg:
+    maxItems: 1
+    description: Should specify the base address for the PCIe PDC device.
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  # Example of PCIE PDC device
+  - |
+    pcie_pdc: pdc@b350000 {
+      compatible = "qcom,pineapple-pcie-pdc", "qcom,pcie-pdc";
+      reg = <0xb350000 0x20000>;
+    };
+...