From 704e2e0186fd23d21aa90bc494724c537f92c28a Mon Sep 17 00:00:00 2001
From: Melody Olvera <quic_molvera@quicinc.com>
Date: Wed, 15 Nov 2023 16:12:24 -0800
Subject: [PATCH] ARM: dts: msm: sun: Update arch and memtimer frequencies

Arch timer and memtimer frequencies were set incorrectly for
silicon, so set to 1 GHz.

Change-Id: I309c1d79712145a4c86d168d923f91d6a6792142
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 qcom/sun.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index 3af86407..f6a4baed 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -734,7 +734,7 @@
 		ranges;
 		compatible = "arm,armv7-timer-mem";
 		reg = <0x16800000 0x1000>;
-		clock-frequency = <19200000>;
+		clock-frequency = <1000000000>;
 
 		frame@16801000 {
 			frame-number = <0>;
@@ -843,7 +843,7 @@
 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
-		clock-frequency = <19200000>;
+		clock-frequency = <1000000000>;
 	};
 
 	pcie_crm_hw_0_bcm_voter: bcm_voter@0 {