From 56dbbd2fdd83e2fe11217ceec725ad231345f426 Mon Sep 17 00:00:00 2001
From: Mike Tipton <quic_mdtipton@quicinc.com>
Date: Fri, 26 Jan 2024 06:46:48 -0800
Subject: [PATCH 1/2] dt-bindings: cpufreq: Add qcom,cpufreq-thermal docs

Add documentation for the qcom,cpufreq-thermal device, which is used to
handle CPU thermal limit mailboxes notifications.

Change-Id: I6e2c33d2a9d55ab4bb2c8361091ebb0110739d43
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
---
 bindings/cpufreq/cpufreq-qcom-thermal.yaml | 47 ++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 bindings/cpufreq/cpufreq-qcom-thermal.yaml

diff --git a/bindings/cpufreq/cpufreq-qcom-thermal.yaml b/bindings/cpufreq/cpufreq-qcom-thermal.yaml
new file mode 100644
index 00000000..8a75dad8
--- /dev/null
+++ b/bindings/cpufreq/cpufreq-qcom-thermal.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. CPUFREQ Thermal
+
+maintainers:
+  - Mike Tipton <quic_mdtipton@quicinc.com>
+
+description: |
+
+  This device listens for CPU thermal frequency limit mailbox notifications and
+  informs the scheduler of them via thermal pressure.
+
+properties:
+  compatible:
+    const: qcom,cpufreq-thermal
+
+  mboxes:
+    description: Mailboxes used for each cpufreq policy
+
+  qcom,policy-cpus:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: Base CPU indices for each cpufreq policy
+
+required:
+  - compatible
+  - mboxes
+  - qcom,policy-cpus
+
+additionalProperties: false
+
+examples:
+  - |
+    // Two clusters. The first cluster starts with CPU0, and the second cluster
+    // starts with CPU6. The mailboxes for each cluster are indexes 5 and 6 of
+    // the cpucp device.
+    soc {
+      cpufreq_thermal: qcom,cpufreq-thermal {
+        compatible = "qcom,cpufreq-thermal";
+        mboxes = <&cpucp 5>, <&cpucp 6>;
+        qcom,policy-cpus = <0 6>;
+      };
+    };
+...

From baa9d42f027ec29d2b4a0b9289f4a20c5a113efa Mon Sep 17 00:00:00 2001
From: Mike Tipton <quic_mdtipton@quicinc.com>
Date: Mon, 22 Jan 2024 08:56:39 -0800
Subject: [PATCH 2/2] ARM: dts: msm: Add cpufreq_thermal device for Sun

This device is necessary to notify the scheduler about CPU thermal
pressure.

Change-Id: Ibf1e636dfee32ab8b7c3b9202264603d638c577a
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
---
 qcom/sun.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index b394d74e..bc0dcb29 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -1614,6 +1614,12 @@
 			  "cdsp", "apss";
 	};
 
+	cpufreq_thermal: qcom,cpufreq-thermal {
+		compatible = "qcom,cpufreq-thermal";
+		mboxes = <&cpucp 5>, <&cpucp 6>;
+		qcom,policy-cpus = <0 6>;
+	};
+
 	cambistmclkcc: clock-controller@1760000 {
 		compatible = "qcom,sun-cambistmclkcc", "syscon";
 		reg = <0x1760000 0x6000>;