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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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96
bindings/watchdog/allwinner,sun4i-a10-wdt.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/allwinner,sun4i-a10-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Watchdog
allOf:
- $ref: "watchdog.yaml#"
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
oneOf:
- const: allwinner,sun4i-a10-wdt
- const: allwinner,sun6i-a31-wdt
- items:
- enum:
- allwinner,sun50i-a64-wdt
- allwinner,sun50i-a100-wdt
- allwinner,sun50i-h6-wdt
- allwinner,sun50i-h616-wdt
- allwinner,sun50i-r329-wdt
- allwinner,sun50i-r329-wdt-reset
- allwinner,suniv-f1c100s-wdt
- const: allwinner,sun6i-a31-wdt
- const: allwinner,sun20i-d1-wdt
- items:
- const: allwinner,sun20i-d1-wdt-reset
- const: allwinner,sun20i-d1-wdt
reg:
maxItems: 1
clocks:
minItems: 1
items:
- description: 32 KHz input clock
- description: secondary clock source
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
- interrupts
if:
properties:
compatible:
contains:
enum:
- allwinner,sun20i-d1-wdt
- allwinner,sun20i-d1-wdt-reset
- allwinner,sun50i-r329-wdt
- allwinner,sun50i-r329-wdt-reset
then:
properties:
clocks:
items:
- description: High-frequency oscillator input, divided internally
- description: Low-frequency oscillator input
clock-names:
items:
- const: hosc
- const: losc
required:
- clock-names
else:
properties:
clocks:
maxItems: 1
unevaluatedProperties: false
examples:
- |
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
interrupts = <24>;
clocks = <&osc24M>;
timeout-sec = <10>;
};
...

35
bindings/watchdog/alphascale-asm9260.txt Normal file
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Alphascale asm9260 Watchdog timer
Required properties:
- compatible : should be "alphascale,asm9260-wdt".
- reg : Specifies base physical address and size of the registers.
- clocks : the clocks feeding the watchdog timer. See clock-bindings.txt
- clock-names : should be set to
"mod" - source for tick counter.
"ahb" - ahb gate.
- resets : phandle pointing to the system reset controller with
line index for the watchdog.
- reset-names : should be set to "wdt_rst".
Optional properties:
- timeout-sec : shall contain the default watchdog timeout in seconds,
if unset, the default timeout is 30 seconds.
- alphascale,mode : three modes are supported
"hw" - hw reset (default).
"sw" - sw reset.
"debug" - no action is taken.
Example:
watchdog0: watchdog@80048000 {
compatible = "alphascale,asm9260-wdt";
reg = <0x80048000 0x10>;
clocks = <&acc CLKID_SYS_WDT>, <&acc CLKID_AHB_WDT>;
clock-names = "mod", "ahb";
interrupts = <55>;
resets = <&rst WDT_RESET>;
reset-names = "wdt_rst";
timeout-sec = <30>;
alphascale,mode = "hw";
};

42
bindings/watchdog/amlogic,meson-gxbb-wdt.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/watchdog/amlogic,meson-gxbb-wdt.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Meson GXBB SoCs Watchdog timer
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
enum:
- amlogic,meson-gxbb-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
description:
A phandle to the clock of this PHY
required:
- compatible
- reg
- clocks
unevaluatedProperties: false
examples:
- |
watchdog@98d0 {
compatible = "amlogic,meson-gxbb-wdt";
reg = <0x98d0 0x10>;
clocks = <&xtal>;
};

52
bindings/watchdog/apple,wdt.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/apple,wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple SoC Watchdog
allOf:
- $ref: "watchdog.yaml#"
maintainers:
- Sven Peter <sven@svenpeter.dev>
properties:
compatible:
items:
- enum:
- apple,t8103-wdt
- apple,t6000-wdt
- const: apple,wdt
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
wdt: watchdog@50000000 {
compatible = "apple,t8103-wdt", "apple,wdt";
reg = <0x50000000 0x4000>;
clocks = <&clk>;
interrupts = <AIC_IRQ 123 IRQ_TYPE_LEVEL_HIGH>;
};
...

51
bindings/watchdog/arm,sbsa-gwdt.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/arm,sbsa-gwdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SBSA (Server Base System Architecture) Generic Watchdog
maintainers:
- Fu Wei <fu.wei@linaro.org>
description: |
The SBSA Generic Watchdog Timer is used to force a reset of the system after
two stages of timeout have elapsed. A detailed definition of the watchdog
timer can be found in the ARM document: ARM-DEN-0029 - Server Base System
Architecture (SBSA)
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
const: arm,sbsa-gwdt
reg:
items:
- description: Watchdog control frame
- description: Refresh frame
interrupts:
description: The Watchdog Signal 0 (WS0) SPI (Shared Peripheral Interrupt)
maxItems: 1
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
watchdog@2a440000 {
compatible = "arm,sbsa-gwdt";
reg = <0x2a440000 0x1000>,
<0x2a450000 0x1000>;
interrupts = <0 27 4>;
timeout-sec = <30>;
};
...

71
bindings/watchdog/arm,sp805.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/arm,sp805.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM AMBA Primecell SP805 Watchdog
maintainers:
- Viresh Kumar <vireshk@kernel.org>
description: |+
The Arm SP805 IP implements a watchdog device, which triggers an interrupt
after a configurable time period. If that interrupt has not been serviced
when the next interrupt would be triggered, the reset signal is asserted.
allOf:
- $ref: /schemas/watchdog/watchdog.yaml#
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,sp805
required:
- compatible
properties:
compatible:
items:
- const: arm,sp805
- const: arm,primecell
interrupts:
maxItems: 1
reg:
maxItems: 1
clocks:
description: |
Clocks driving the watchdog timer hardware. The first clock is used
for the actual watchdog counter. The second clock drives the register
interface.
minItems: 2
maxItems: 2
clock-names:
items:
- const: wdog_clk
- const: apb_pclk
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
watchdog@66090000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x66090000 0x1000>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wdt_clk>, <&apb_pclk>;
clock-names = "wdog_clk", "apb_pclk";
};

50
bindings/watchdog/arm,twd-wdt.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Timer-Watchdog Watchdog
maintainers:
- Rob Herring <robh@kernel.org>
description:
ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
and watchdog.
The TWD is usually attached to a GIC to deliver its two per-processor
interrupts.
properties:
compatible:
enum:
- arm,cortex-a9-twd-wdt
- arm,cortex-a5-twd-wdt
- arm,arm11mp-twd-wdt
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
watchdog@2c000620 {
compatible = "arm,arm11mp-twd-wdt";
reg = <0x2c000620 0x20>;
interrupts = <GIC_PPI 14 0xf01>;
};

38
bindings/watchdog/arm-smc-wdt.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/arm-smc-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Secure Monitor Call based watchdog
allOf:
- $ref: "watchdog.yaml#"
maintainers:
- Julius Werner <jwerner@chromium.org>
properties:
compatible:
enum:
- arm,smc-wdt
arm,smc-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The ATF smc function id used by the firmware.
Defaults to 0x82003D06 if unset.
required:
- compatible
unevaluatedProperties: false
examples:
- |
watchdog {
compatible = "arm,smc-wdt";
arm,smc-id = <0x82003D06>;
timeout-sec = <15>;
};
...

23
bindings/watchdog/armada-37xx-wdt.txt Normal file
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* Armada 37xx CPU Watchdog Timer Controller
Required properties:
- compatible : must be "marvell,armada-3700-wdt"
- reg : base physical address of the controller and length of memory mapped
region.
- clocks : the clock feeding the watchdog timer. See clock-bindings.txt
- marvell,system-controller : reference to syscon node for the CPU Miscellaneous
Registers
Example:
cpu_misc: system-controller@d000 {
compatible = "marvell,armada-3700-cpu-misc", "syscon";
reg = <0xd000 0x1000>;
};
wdt: watchdog@8300 {
compatible = "marvell,armada-3700-wdt";
reg = <0x8300 0x40>;
marvell,system-controller = <&cpu_misc>;
clocks = <&xtalclk>;
};

57
bindings/watchdog/aspeed-wdt.txt Normal file
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Aspeed Watchdog Timer
Required properties:
- compatible: must be one of:
- "aspeed,ast2400-wdt"
- "aspeed,ast2500-wdt"
- "aspeed,ast2600-wdt"
- reg: physical base address of the controller and length of memory mapped
region
Optional properties:
- aspeed,reset-type = "cpu|soc|system|none"
Reset behavior - Whenever a timeout occurs the watchdog can be programmed
to generate one of three different, mutually exclusive, types of resets.
Type "none" can be specified to indicate that no resets are to be done.
This is useful in situations where another watchdog engine on chip is
to perform the reset.
If 'aspeed,reset-type=' is not specified the default is to enable system
reset.
Reset types:
- cpu: Reset CPU on watchdog timeout
- soc: Reset 'System on Chip' on watchdog timeout
- system: Reset system on watchdog timeout
- none: No reset is performed on timeout. Assumes another watchdog
engine is responsible for this.
- aspeed,alt-boot: If property is present then boot from alternate block.
- aspeed,external-signal: If property is present then signal is sent to
external reset counter (only WDT1 and WDT2). If not
specified no external signal is sent.
- aspeed,ext-pulse-duration: External signal pulse duration in microseconds
Optional properties for AST2500-compatible watchdogs:
- aspeed,ext-push-pull: If aspeed,external-signal is present, set the pin's
drive type to push-pull. The default is open-drain.
- aspeed,ext-active-high: If aspeed,external-signal is present and and the pin
is configured as push-pull, then set the pulse
polarity to active-high. The default is active-low.
Example:
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785000 0x1c>;
aspeed,reset-type = "system";
aspeed,external-signal;
};

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bindings/watchdog/atmel,at91sam9-wdt.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/atmel,at91sam9-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Watchdog Timers
maintainers:
- Eugen Hristev <eugen.hristev@microchip.com>
properties:
compatible:
const: atmel,at91sam9260-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
atmel,max-heartbeat-sec:
description:
Should contain the maximum heartbeat value in seconds. This value
should be less or equal to 16. It is used to compute the WDV field.
maximum: 16
atmel,min-heartbeat-sec:
description:
Should contain the minimum heartbeat value in seconds. This value
must be smaller than the max-heartbeat-sec value. It is used to
compute the WDD field.
maximum: 16
atmel,watchdog-type:
$ref: /schemas/types.yaml#/definitions/string
description: |
Should be hardware or software.
oneOf:
- description:
Hardware watchdog uses the at91 watchdog reset.
const: hardware
- description: |
Software watchdog uses the watchdog interrupt
to trigger a software reset.
const: software
default: hardware
atmel,reset-type:
$ref: /schemas/types.yaml#/definitions/string
description: |
Should be proc or all. This is valid only when using hardware watchdog.
oneOf:
- description:
Assert peripherals and processor reset signals.
const: all
- description:
Assert the processor reset signal.
const: proc
default: all
atmel,disable:
$ref: /schemas/types.yaml#/definitions/flag
description:
Should be present if you want to stop the watchdog.
atmel,idle-halt:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Should be present if you want to stop the watchdog when
entering idle state.
CAUTION: This property should be used with care, it actually makes the
watchdog not counting when the CPU is in idle state, therefore the
watchdog reset time depends on mean CPU usage and will not reset at all
if the CPU stops working while it is in idle state, which is probably
not what you want.
atmel,dbg-halt:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Should be present if you want to stop the watchdog when
entering debug state.
required:
- compatible
- reg
- clocks
allOf:
- $ref: watchdog.yaml#
- if:
properties:
atmel,reset-type:
enum:
- all
- proc
then:
properties:
atmel,watchdog-type:
const: hardware
dependencies:
atmel,reset-type: ['atmel,watchdog-type']
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
timeout-sec = <15>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
atmel,max-heartbeat-sec = <16>;
atmel,min-heartbeat-sec = <0>;
};

77
bindings/watchdog/atmel,sama5d4-wdt.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/atmel,sama5d4-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel SAMA5D4 Watchdog Timer (WDT) Controller
maintainers:
- Eugen Hristev <eugen.hristev@microchip.com>
allOf:
- $ref: "watchdog.yaml#"
properties:
compatible:
enum:
- atmel,sama5d4-wdt
- microchip,sam9x60-wdt
- microchip,sama7g5-wdt
reg:
maxItems: 1
interrupts:
maxItems: 1
atmel,watchdog-type:
$ref: /schemas/types.yaml#/definitions/string
description: should be hardware or software.
oneOf:
- description:
Enable watchdog fault reset. A watchdog fault triggers
watchdog reset.
const: hardware
- description:
Enable watchdog fault interrupt. A watchdog fault asserts
watchdog interrupt.
const: software
default: hardware
atmel,idle-halt:
$ref: /schemas/types.yaml#/definitions/flag
description: |
present if you want to stop the watchdog when the CPU is in idle state.
CAUTION: This property should be used with care, it actually makes the
watchdog not counting when the CPU is in idle state, therefore the
watchdog reset time depends on mean CPU usage and will not reset at all
if the CPU stop working while it is in idle state, which is probably
not what you want.
atmel,dbg-halt:
$ref: /schemas/types.yaml#/definitions/flag
description: |
present if you want to stop the watchdog when the CPU is in debug state.
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
watchdog@fc068640 {
compatible = "atmel,sama5d4-wdt";
reg = <0xfc068640 0x10>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
timeout-sec = <10>;
atmel,watchdog-type = "hardware";
atmel,dbg-halt;
atmel,idle-halt;
};
...

9
bindings/watchdog/atmel-at91rm9200-wdt.txt Normal file
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Atmel AT91RM9200 System Timer Watchdog
Required properties:
- compatible: must be "atmel,at91sam9260-wdt".
Example:
watchdog@fffffd00 {
compatible = "atmel,at91rm9200-wdt";
};

18
bindings/watchdog/brcm,bcm2835-pm-wdog.txt Normal file
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BCM2835 Watchdog timer
Required properties:
- compatible : should be "brcm,bcm2835-pm-wdt"
- reg : Specifies base physical address and size of the registers.
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
Example:
watchdog {
compatible = "brcm,bcm2835-pm-wdt";
reg = <0x7e100000 0x28>;
timeout-sec = <10>;
};

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bindings/watchdog/brcm,bcm7038-wdt.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/brcm,bcm7038-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: BCM63xx and BCM7038 watchdog timer
allOf:
- $ref: "watchdog.yaml#"
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
- Justin Chen <justinpopo6@gmail.com>
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
enum:
- brcm,bcm6345-wdt
- brcm,bcm7038-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
description: >
The clock running the watchdog. If no clock is found the driver will
default to 27000000 Hz.
unevaluatedProperties: false
required:
- reg
examples:
- |
watchdog@f040a7e8 {
compatible = "brcm,bcm7038-wdt";
reg = <0xf040a7e8 0x16>;
clocks = <&upg_fixed>;
};

15
bindings/watchdog/brcm,kona-wdt.txt Normal file
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Broadcom Kona Family Watchdog Timer
-----------------------------------
This watchdog timer is used in the following Broadcom SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155
Required properties:
- compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
- reg: memory address & range
Example:
watchdog@35002f40 {
compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
reg = <0x35002f40 0x6c>;
};

23
bindings/watchdog/cadence-wdt.txt Normal file
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Zynq Watchdog Device Tree Bindings
-------------------------------------------
Required properties:
- compatible : Should be "cdns,wdt-r1p2".
- clocks : This is pclk (APB clock).
- interrupts : This is wd_irq - watchdog timeout interrupt.
Optional properties
- reset-on-timeout : If this property exists, then a reset is done
when watchdog times out.
- timeout-sec : Watchdog timeout value (in seconds).
Example:
watchdog@f8005000 {
compatible = "cdns,wdt-r1p2";
clocks = <&clkc 45>;
interrupt-parent = <&intc>;
interrupts = <0 9 1>;
reg = <0xf8005000 0x1000>;
reset-on-timeout;
timeout-sec = <10>;
};

34
bindings/watchdog/da9062-wdt.txt Normal file
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* Dialog Semiconductor DA9062/61 Watchdog Timer
Required properties:
- compatible: should be one of the following valid compatible string lines:
"dlg,da9061-watchdog", "dlg,da9062-watchdog"
"dlg,da9062-watchdog"
Optional properties:
- dlg,use-sw-pm: Add this property to disable the watchdog during suspend.
Only use this option if you can't use the watchdog automatic suspend
function during a suspend (see register CONTROL_B).
- dlg,wdt-sd: Set what happens on watchdog timeout. If this bit is set the
watchdog timeout triggers SHUTDOWN, if cleared the watchdog triggers
POWERDOWN. Can be 0 or 1. Only use this option if you want to change the
default chip's OTP setting for WATCHDOG_SD bit. If this property is NOT
set the WATCHDOG_SD bit and on timeout watchdog behavior will match the
chip's OTP settings.
Example: DA9062
pmic0: da9062@58 {
watchdog {
compatible = "dlg,da9062-watchdog";
};
};
Example: DA9061 using a fall-back compatible for the DA9062 watchdog driver
pmic0: da9061@58 {
watchdog {
compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog";
};
};

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Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
Required properties:
- compatible : Should be "ti,davinci-wdt", "ti,keystone-wdt"
- reg : Should contain WDT registers location and length
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
- clocks : the clock feeding the watchdog timer.
Needed if platform uses clocks.
See clock-bindings.txt
Documentation:
Davinci DM646x - https://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
Keystone - https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Examples:
wdt: wdt@2320000 {
compatible = "ti,davinci-wdt";
reg = <0x02320000 0x80>;
timeout-sec = <30>;
clocks = <&clkwdtimer0>;
};

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Conexant Digicolor SoCs Watchdog timer
The watchdog functionality in Conexant Digicolor SoCs relies on the so called
"Agent Communication" block. This block includes the eight programmable system
timer counters. The first timer (called "Timer A") is the only one that can be
used as watchdog.
Required properties:
- compatible : Should be "cnxt,cx92755-wdt"
- reg : Specifies base physical address and size of the registers
- clocks : phandle; specifies the clock that drives the timer
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
Example:
watchdog@f0000fc0 {
compatible = "cnxt,cx92755-wdt";
reg = <0xf0000fc0 0x8>;
clocks = <&main_clk>;
timeout-sec = <15>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/faraday,ftwdt010.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Faraday Technology FTWDT010 watchdog
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Corentin Labbe <clabbe@baylibre.com>
description: |
This is an IP part from Faraday Technology found in the Gemini
SoCs and others.
allOf:
- $ref: "watchdog.yaml#"
properties:
compatible:
oneOf:
- const: faraday,ftwdt010
- items:
- enum:
- cortina,gemini-watchdog
- moxa,moxart-watchdog
- const: faraday,ftwdt010
reg:
maxItems: 1
resets:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: PCLK
interrupts:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
watchdog@41000000 {
compatible = "faraday,ftwdt010";
reg = <0x41000000 0x1000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <5>;
};
- |
watchdog: watchdog@98500000 {
compatible = "moxa,moxart-watchdog", "faraday,ftwdt010";
reg = <0x98500000 0x10>;
clocks = <&clk_apb>;
clock-names = "PCLK";
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/fsl,scu-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX SCU Client Device Node - Watchdog bindings based on SCU Message Protocol
maintainers:
- Dong Aisheng <aisheng.dong@nxp.com>
description: i.MX SCU Client Device Node
Client nodes are maintained as children of the relevant IMX-SCU device node.
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
items:
- const: fsl,imx8qxp-sc-wdt
- const: fsl,imx-sc-wdt
required:
- compatible
unevaluatedProperties: false
examples:
- |
watchdog {
compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
timeout-sec = <60>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/fsl-imx-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX Watchdog Timer (WDT) Controller
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
allOf:
- $ref: "watchdog.yaml#"
properties:
compatible:
oneOf:
- const: fsl,imx21-wdt
- items:
- enum:
- fsl,imx25-wdt
- fsl,imx27-wdt
- fsl,imx31-wdt
- fsl,imx35-wdt
- fsl,imx50-wdt
- fsl,imx51-wdt
- fsl,imx53-wdt
- fsl,imx6q-wdt
- fsl,imx6sl-wdt
- fsl,imx6sll-wdt
- fsl,imx6sx-wdt
- fsl,imx6ul-wdt
- fsl,imx7d-wdt
- fsl,imx8mm-wdt
- fsl,imx8mn-wdt
- fsl,imx8mp-wdt
- fsl,imx8mq-wdt
- fsl,ls1012a-wdt
- fsl,ls1043a-wdt
- fsl,vf610-wdt
- const: fsl,imx21-wdt
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
fsl,ext-reset-output:
$ref: /schemas/types.yaml#/definitions/flag
description: |
If present, the watchdog device is configured to assert its
external reset (WDOG_B) instead of issuing a software reset.
required:
- compatible
- interrupts
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
watchdog@20bc000 {
compatible = "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_IPG>;
};
...

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX7ULP Watchdog Timer (WDT) Controller
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
allOf:
- $ref: "watchdog.yaml#"
properties:
compatible:
oneOf:
- const: fsl,imx7ulp-wdt
- items:
- const: fsl,imx8ulp-wdt
- const: fsl,imx7ulp-wdt
- const: fsl,imx93-wdt
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
timeout-sec: true
required:
- compatible
- interrupts
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imx7ulp-clock.h>
watchdog@403d0000 {
compatible = "fsl,imx7ulp-wdt";
reg = <0x403d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
timeout-sec = <40>;
};
...

28
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* GPIO-controlled Watchdog
Required Properties:
- compatible: Should contain "linux,wdt-gpio".
- gpios: From common gpio binding; gpio connection to WDT reset pin.
- hw_algo: The algorithm used by the driver. Should be one of the
following values:
- toggle: Either a high-to-low or a low-to-high transition clears
the WDT counter. The watchdog timer is disabled when GPIO is
left floating or connected to a three-state buffer.
- level: Low or high level starts counting WDT timeout,
the opposite level disables the WDT. Active level is determined
by the GPIO flags.
- hw_margin_ms: Maximum time to reset watchdog circuit (milliseconds).
Optional Properties:
- always-running: If the watchdog timer cannot be disabled, add this flag to
have the driver keep toggling the signal without a client. It will only cease
to toggle the signal when the device is open and the timeout elapsed.
Example:
watchdog: watchdog {
/* ADM706 */
compatible = "linux,wdt-gpio";
gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
hw_algo = "toggle";
hw_margin_ms = <1600>;
};

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*ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT)
Required properties:
- compatible : Should be "img,pdc-wdt"
- reg : Should contain WDT registers location and length
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Should contain "wdt" and "sys"; the watchdog counter
clock and register interface clock respectively.
- interrupts : Should contain WDT interrupt
Examples:
watchdog@18102100 {
compatible = "img,pdc-wdt";
reg = <0x18102100 0x100>;
clocks = <&pdc_wdt_clk>, <&sys_clk>;
clock-names = "wdt", "sys";
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/intel,keembay-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Keem Bay SoC non-secure Watchdog Timer
maintainers:
- Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
properties:
compatible:
enum:
- intel,keembay-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
items:
- description: interrupt specifier for threshold interrupt line
- description: interrupt specifier for timeout interrupt line
interrupt-names:
items:
- const: threshold
- const: timeout
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define KEEM_BAY_A53_TIM
watchdog: watchdog@2033009c {
compatible = "intel,keembay-wdt";
reg = <0x2033009c 0x10>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "threshold", "timeout";
clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
};
...

35
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/kontron,sl28cpld-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Watchdog driver for the sl28cpld board management controller
maintainers:
- Michael Walle <michael@walle.cc>
description: |
This module is part of the sl28cpld multi-function device. For more
details see ../mfd/kontron,sl28cpld.yaml.
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
const: kontron,sl28cpld-wdt
reg:
maxItems: 1
kontron,assert-wdt-timeout-pin:
description: The SMARC standard defines a WDT_TIME_OUT# pin. If this
property is set, this output will be pulsed when the watchdog bites
and the system resets.
type: boolean
required:
- compatible
additionalProperties: false

24
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Lantiq WTD watchdog binding
============================
This describes the binding of the Lantiq watchdog driver.
-------------------------------------------------------------------------------
Required properties:
- compatible : Should be one of
"lantiq,wdt"
"lantiq,xrx100-wdt"
"lantiq,xrx200-wdt", "lantiq,xrx100-wdt"
"lantiq,falcon-wdt"
- reg : Address of the watchdog block
- lantiq,rcu : A phandle to the RCU syscon (required for
"lantiq,falcon-wdt" and "lantiq,xrx100-wdt")
-------------------------------------------------------------------------------
Example for the watchdog on the xRX200 SoCs:
watchdog@803f0 {
compatible = "lantiq,xrx200-wdt", "lantiq,xrx100-wdt";
reg = <0x803f0 0x10>;
lantiq,rcu = <&rcu0>;
};

19
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* NXP LPC18xx Watchdog Timer (WDT)
Required properties:
- compatible: Should be "nxp,lpc1850-wwdt"
- reg: Should contain WDT registers location and length
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Should contain "wdtclk" and "reg"; the watchdog counter
clock and register interface clock respectively.
- interrupts: Should contain WDT interrupt
Examples:
watchdog@40080000 {
compatible = "nxp,lpc1850-wwdt";
reg = <0x40080000 0x24>;
clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
clock-names = "wdtclk", "reg";
interrupts = <49>;
};

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* Marvell Orion Watchdog Time
Required Properties:
- Compatibility : "marvell,orion-wdt"
"marvell,armada-370-wdt"
"marvell,armada-xp-wdt"
"marvell,armada-375-wdt"
"marvell,armada-380-wdt"
- reg : Should contain two entries: first one with the
timer control address, second one with the
rstout enable address.
For "marvell,armada-375-wdt" and "marvell,armada-380-wdt":
- reg : A third entry is mandatory and should contain the
shared mask/unmask RSTOUT address.
Clocks required for compatibles = "marvell,orion-wdt",
"marvell,armada-370-wdt":
- clocks : Must contain a single entry describing the clock input
Clocks required for compatibles = "marvell,armada-xp-wdt"
"marvell,armada-375-wdt"
"marvell,armada-380-wdt":
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"nbclk" (L2/coherency fabric clock),
"fixed" (Reference 25 MHz fixed-clock).
Optional properties:
- interrupts : Contains the IRQ for watchdog expiration
- timeout-sec : Contains the watchdog timeout in seconds
Example:
wdt@20300 {
compatible = "marvell,orion-wdt";
reg = <0x20300 0x28>, <0x20108 0x4>;
interrupts = <3>;
timeout-sec = <10>;
clocks = <&gate_clk 7>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/maxim,max63xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim 63xx Watchdog Timers
allOf:
- $ref: "watchdog.yaml#"
maintainers:
- Marc Zyngier <maz@kernel.org>
- Linus Walleij <linus.walleij@linaro.org>
properties:
compatible:
enum:
- maxim,max6369
- maxim,max6370
- maxim,max6371
- maxim,max6372
- maxim,max6373
- maxim,max6374
reg:
description: This is a 1-byte memory-mapped address
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
wdt: watchdog@50000000 {
compatible = "maxim,max6369";
reg = <0x50000000 0x1>;
timeout-sec = <10>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/mediatek,mt7621-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ralink Watchdog Timers
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
const: mediatek,mt7621-wdt
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
watchdog@100 {
compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};

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Bindings for MEN A21 Watchdog device connected to GPIO lines
Required properties:
- compatible: "men,a021-wdt"
- gpios: Specifies the pins that control the Watchdog, order:
1: Watchdog enable
2: Watchdog fast-mode
3: Watchdog trigger
4: Watchdog reset cause bit 0
5: Watchdog reset cause bit 1
6: Watchdog reset cause bit 2
Optional properties:
- None
Example:
watchdog {
compatible ="men,a021-wdt";
gpios = <&gpio3 9 1 /* WD_EN */
&gpio3 10 1 /* WD_FAST */
&gpio3 11 1 /* WD_TRIG */
&gpio3 6 1 /* RST_CAUSE[0] */
&gpio3 7 1 /* RST_CAUSE[1] */
&gpio3 8 1>; /* RST_CAUSE[2] */
};

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Meson SoCs Watchdog timer
Required properties:
- compatible : depending on the SoC this should be one of:
"amlogic,meson6-wdt" on Meson6 SoCs
"amlogic,meson8-wdt" and "amlogic,meson6-wdt" on Meson8 SoCs
"amlogic,meson8b-wdt" on Meson8b SoCs
"amlogic,meson8m2-wdt" and "amlogic,meson8b-wdt" on Meson8m2 SoCs
- reg : Specifies base physical address and size of the registers.
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.
Example:
wdt: watchdog@c1109900 {
compatible = "amlogic,meson6-wdt";
reg = <0xc1109900 0x8>;
timeout-sec = <10>;
};

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* Microchip PIC32 Deadman Timer
The deadman timer is used to reset the processor in the event of a software
malfunction. It is a free-running instruction fetch timer, which is clocked
whenever an instruction fetch occurs until a count match occurs.
Required properties:
- compatible: must be "microchip,pic32mzda-dmt".
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: phandle of source clk. Should be <&rootclk PB7CLK>.
Example:
watchdog@1f800a00 {
compatible = "microchip,pic32mzda-dmt";
reg = <0x1f800a00 0x80>;
clocks = <&rootclk PB7CLK>;
};

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* Microchip PIC32 Watchdog Timer
When enabled, the watchdog peripheral can be used to reset the device if the
WDT is not cleared periodically in software.
Required properties:
- compatible: must be "microchip,pic32mzda-wdt".
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: phandle of source clk. Should be <&rootclk LPRCCLK>.
Example:
watchdog@1f800800 {
compatible = "microchip,pic32mzda-wdt";
reg = <0x1f800800 0x200>;
clocks = <&rootclk LPRCCLK>;
};

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bindings/watchdog/moxa,moxart-watchdog.txt Normal file
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MOXA ART Watchdog timer
Required properties:
- compatible : Must be "moxa,moxart-watchdog"
- reg : Should contain registers location and length
- clocks : Should contain phandle for the clock that drives the counter
Example:
watchdog: watchdog@98500000 {
compatible = "moxa,moxart-watchdog";
reg = <0x98500000 0x10>;
clocks = <&coreclk>;
};

25
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* Freescale mpc8xxx watchdog driver (For 83xx, 86xx and 8xx)
Required properties:
- compatible: Shall contain one of the following:
"mpc83xx_wdt" for an mpc83xx
"fsl,mpc8610-wdt" for an mpc86xx
"fsl,mpc823-wdt" for an mpc8xx
- reg: base physical address and length of the area hosting the
watchdog registers.
On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
On the 8xx, "General System Interface Unit" area: <0x0 0x10>
Optional properties:
- reg: additional physical address and length (4) of location of the
Reset Status Register (called RSTRSCR on the mpc86xx)
On the 83xx, it is located at offset 0x910
On the 86xx, it is located at offset 0xe0094
On the 8xx, it is located at offset 0x288
Example:
WDT: watchdog@0 {
compatible = "fsl,mpc823-wdt";
reg = <0x0 0x10 0x288 0x4>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/mstar,msc313e-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar Watchdog
maintainers:
- Daniel Palmer <daniel@0x0f.com>
- Romain Perier <romain.perier@gmail.com>
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
enum:
- mstar,msc313e-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- clocks
- reg
unevaluatedProperties: false
examples:
- |
watchdog@6000 {
compatible = "mstar,msc313e-wdt";
reg = <0x6000 0x1f>;
clocks = <&xtal_div2>;
};

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Mediatek SoCs Watchdog timer
The watchdog supports a pre-timeout interrupt that fires timeout-sec/2
before the expiry.
Required properties:
- compatible should contain:
"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
"mediatek,mt2712-wdt": for MT2712
"mediatek,mt6582-wdt", "mediatek,mt6589-wdt": for MT6582
"mediatek,mt6589-wdt": for MT6589
"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8186-wdt", "mediatek,mt6589-wdt": for MT8186
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
"mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
- reg : Specifies base physical address and size of the registers.
Optional properties:
- mediatek,disable-extrst: disable send output reset signal
- interrupts: Watchdog pre-timeout (bark) interrupt.
- timeout-sec: contains the watchdog timeout in seconds.
- #reset-cells: Should be 1.
Example:
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8183-wdt",
"mediatek,mt6589-wdt";
mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
timeout-sec = <10>;
#reset-cells = <1>;
};

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Nuvoton NPCM Watchdog
Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog.
The watchdog supports a pre-timeout interrupt that fires 10ms before the
expiry.
Required properties:
- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
"nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or
"nuvoton,npcm845-wdt" for NPCM845 (Arbel).
- reg : Offset and length of the register set for the device.
- interrupts : Contain the timer interrupt with flags for
falling edge.
Required clocking property, have to be one of:
- clocks : phandle of timer reference clock.
- clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx
timer (usually 25000000).
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
Example:
timer@f000801c {
compatible = "nuvoton,npcm750-wdt";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf000801c 0x4>;
clocks = <&clk NPCM7XX_CLK_TIMER>;
};

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TI Watchdog Timer (WDT) Controller for OMAP
Required properties:
- compatible : "ti,omap3-wdt" for OMAP3 or "ti,omap4-wdt" for OMAP4
- ti,hwmods : Name of the hwmod associated to the WDT
Optional properties:
- timeout-sec : default watchdog timeout in seconds
Examples:
wdt2: wdt@4a314000 {
compatible = "ti,omap4-wdt", "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
};

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* NXP PNX watchdog timer
Required properties:
- compatible: must be "nxp,pnx4008-wdt"
- reg: physical base address of the controller and length of memory mapped
region.
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.
Example:
watchdog@4003c000 {
compatible = "nxp,pnx4008-wdt";
reg = <0x4003C000 0x1000>;
timeout-sec = <10>;
};

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* Qualcomm Atheros AR7130 Watchdog Timer (WDT) Controller
Required properties:
- compatible: must be "qca,ar7130-wdt"
- reg: physical base address of the controller and length of memory mapped
region.
Example:
wdt@18060008 {
compatible = "qca,ar9330-wdt", "qca,ar7130-wdt";
reg = <0x18060008 0x8>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/qcom,pm8916-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PM8916 watchdog timer controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
const: qcom,pm8916-wdt
interrupts:
maxItems: 1
required:
- compatible
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
pmic@0 {
compatible = "qcom,pm8916", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
watchdog {
compatible = "qcom,pm8916-wdt";
interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>;
timeout-sec = <60>;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
maintainers:
- Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,apss-wdt-qcs404
- qcom,apss-wdt-sc7180
- qcom,apss-wdt-sc7280
- qcom,apss-wdt-sc8180x
- qcom,apss-wdt-sc8280xp
- qcom,apss-wdt-sdm845
- qcom,apss-wdt-sdx55
- qcom,apss-wdt-sdx65
- qcom,apss-wdt-sm6350
- qcom,apss-wdt-sm8150
- qcom,apss-wdt-sm8250
- const: qcom,kpss-wdt
- items:
- enum:
- qcom,kpss-wdt
- qcom,kpss-timer
- qcom,kpss-wdt-apq8064
- qcom,kpss-wdt-ipq4019
- qcom,kpss-wdt-ipq8064
- qcom,kpss-wdt-msm8960
- qcom,scss-timer
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- clocks
unevaluatedProperties: false
examples:
- |
watchdog@208a038 {
compatible = "qcom,kpss-wdt-ipq8064";
reg = <0x0208a038 0x40>;
clocks = <&sleep_clk>;
timeout-sec = <10>;
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek Otto watchdog timer
maintainers:
- Sander Vanheule <sander@svanheule.net>
description: |
The timer has two timeout phases. Both phases have a maximum duration of 32
prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The
minimum duration of each phase is one tick. Each phase can trigger an
interrupt, although the phase 2 interrupt will occur with the system reset.
- Phase 1: During this phase, the WDT can be pinged to reset the timeout.
- Phase 2: Starts after phase 1 has timed out, and only serves to give the
system some time to clean up, or notify others that it's going to reset.
During this phase, pinging the WDT has no effect, and a reset is
unavoidable, unless the WDT is disabled.
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
enum:
- realtek,rtl8380-wdt
- realtek,rtl8390-wdt
- realtek,rtl9300-wdt
- realtek,rtl9310-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
items:
- description: interrupt specifier for pretimeout
- description: interrupt specifier for timeout
interrupt-names:
items:
- const: phase1
- const: phase2
realtek,reset-mode:
$ref: /schemas/types.yaml#/definitions/string
description: |
Specify how the system is reset after a timeout. Defaults to "cpu" if
left unspecified.
oneOf:
- description: Reset the entire chip
const: soc
- description: |
Reset the CPU and IPsec engine, but leave other peripherals untouched
const: cpu
- description: |
Reset the execution pointer, but don't actually reset any hardware
const: software
required:
- compatible
- reg
- clocks
- interrupts
unevaluatedProperties: false
dependencies:
interrupts: [ interrupt-names ]
examples:
- |
watchdog: watchdog@3150 {
compatible = "realtek,rtl8380-wdt";
reg = <0x3150 0xc>;
realtek,reset-mode = "soc";
clocks = <&lxbus_clock>;
timeout-sec = <20>;
interrupt-parent = <&rtlintc>;
interrupt-names = "phase1", "phase2";
interrupts = <19>, <18>;
};
...

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Realtek RTD1295 Watchdog
========================
Required properties:
- compatible : Should be "realtek,rtd1295-watchdog"
- reg : Specifies the physical base address and size of registers
- clocks : Specifies one clock input
Example:
watchdog@98007680 {
compatible = "realtek,rtd1295-watchdog";
reg = <0x98007680 0x100>;
clocks = <&osc27M>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/renesas,wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Watchdog Timer (WDT) Controller
maintainers:
- Wolfram Sang <wsa+renesas@sang-engineering.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,r7s72100-wdt # RZ/A1
- renesas,r7s9210-wdt # RZ/A2
- const: renesas,rza-wdt # RZ/A
- items:
- enum:
- renesas,r9a06g032-wdt # RZ/N1D
- const: renesas,rzn1-wdt # RZ/N1
- items:
- enum:
- renesas,r9a07g043-wdt # RZ/G2UL
- renesas,r9a07g044-wdt # RZ/G2{L,LC}
- renesas,r9a07g054-wdt # RZ/V2L
- const: renesas,rzg2l-wdt
- items:
- enum:
- renesas,r9a09g011-wdt # RZ/V2M
- const: renesas,rzv2m-wdt # RZ/V2M
- items:
- enum:
- renesas,r8a7742-wdt # RZ/G1H
- renesas,r8a7743-wdt # RZ/G1M
- renesas,r8a7744-wdt # RZ/G1N
- renesas,r8a7745-wdt # RZ/G1E
- renesas,r8a77470-wdt # RZ/G1C
- renesas,r8a7790-wdt # R-Car H2
- renesas,r8a7791-wdt # R-Car M2-W
- renesas,r8a7792-wdt # R-Car V2H
- renesas,r8a7793-wdt # R-Car M2-N
- renesas,r8a7794-wdt # R-Car E2
- const: renesas,rcar-gen2-wdt # R-Car Gen2 and RZ/G1
- items:
- enum:
- renesas,r8a774a1-wdt # RZ/G2M
- renesas,r8a774b1-wdt # RZ/G2N
- renesas,r8a774c0-wdt # RZ/G2E
- renesas,r8a774e1-wdt # RZ/G2H
- renesas,r8a7795-wdt # R-Car H3
- renesas,r8a7796-wdt # R-Car M3-W
- renesas,r8a77961-wdt # R-Car M3-W+
- renesas,r8a77965-wdt # R-Car M3-N
- renesas,r8a77970-wdt # R-Car V3M
- renesas,r8a77980-wdt # R-Car V3H
- renesas,r8a77990-wdt # R-Car E3
- renesas,r8a77995-wdt # R-Car D3
- const: renesas,rcar-gen3-wdt # R-Car Gen3 and RZ/G2
- items:
- enum:
- renesas,r8a779a0-wdt # R-Car V3U
- renesas,r8a779f0-wdt # R-Car S4-8
- renesas,r8a779g0-wdt # R-Car V4H
- const: renesas,rcar-gen4-wdt # R-Car Gen4
reg:
maxItems: 1
interrupts:
minItems: 1
items:
- description: Timeout
- description: Parity error
interrupt-names:
minItems: 1
items:
- const: wdt
- const: perrout
clocks:
minItems: 1
items:
- description: Register access clock
- description: Main clock
clock-names:
minItems: 1
items:
- const: pclk
- const: oscclk
power-domains:
maxItems: 1
resets:
maxItems: 1
timeout-sec: true
required:
- compatible
- reg
- interrupts
- clocks
allOf:
- $ref: "watchdog.yaml#"
- if:
not:
properties:
compatible:
contains:
enum:
- renesas,rza-wdt
- renesas,rzn1-wdt
then:
required:
- power-domains
- resets
- if:
properties:
compatible:
contains:
enum:
- renesas,rzg2l-wdt
- renesas,rzv2m-wdt
then:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
required:
- clock-names
else:
properties:
clocks:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- renesas,rzg2l-wdt
then:
properties:
interrupts:
minItems: 2
interrupt-names:
minItems: 2
required:
- interrupt-names
else:
properties:
interrupts:
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/power/r8a7795-sysc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
wdt0: watchdog@e6020000 {
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
reg = <0xe6020000 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 402>;
timeout-sec = <60>;
};

18
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Ralink Watchdog Timers
Required properties:
- compatible: must be "ralink,rt2880-wdt"
- reg: physical base address of the controller and length of the register range
Optional properties:
- interrupts: Specify the INTC interrupt number
Example:
watchdog@120 {
compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>;
interrupt-parent = <&intc>;
interrupts = <1>;
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/samsung-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung SoC Watchdog Timer Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |+
The Samsung's Watchdog controller is used for resuming system operation
after a preset amount of time during which the WDT reset event has not
occurred.
properties:
compatible:
enum:
- samsung,s3c2410-wdt # for S3C2410
- samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
- samsung,exynos5250-wdt # for Exynos5250
- samsung,exynos5420-wdt # for Exynos5420
- samsung,exynos7-wdt # for Exynos7
- samsung,exynos850-wdt # for Exynos850
- samsung,exynosautov9-wdt # for Exynosautov9
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
interrupts:
maxItems: 1
samsung,cluster-index:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Index of CPU cluster on which watchdog is running (in case of Exynos850)
samsung,syscon-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the PMU system controller node (in case of Exynos5250,
Exynos5420, Exynos7 and Exynos850).
required:
- compatible
- clocks
- clock-names
- interrupts
- reg
allOf:
- $ref: watchdog.yaml#
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5250-wdt
- samsung,exynos5420-wdt
- samsung,exynos7-wdt
- samsung,exynos850-wdt
- samsung,exynosautov9-wdt
then:
required:
- samsung,syscon-phandle
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos850-wdt
- samsung,exynosautov9-wdt
then:
properties:
clocks:
items:
- description: Bus clock, used for register interface
- description: Source clock (driving watchdog counter)
clock-names:
items:
- const: watchdog
- const: watchdog_src
samsung,cluster-index:
enum: [0, 1]
required:
- samsung,cluster-index
else:
properties:
clocks:
items:
- description: Bus clock, which is also a source clock
clock-names:
items:
- const: watchdog
samsung,cluster-index: false
unevaluatedProperties: false
examples:
- |
watchdog@101d0000 {
compatible = "samsung,exynos5250-wdt";
reg = <0x101D0000 0x100>;
interrupts = <0 42 0>;
clocks = <&clock 336>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_syscon>;
};

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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/snps,dw-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys Designware Watchdog Timer
allOf:
- $ref: "watchdog.yaml#"
maintainers:
- Jamie Iles <jamie@jamieiles.com>
properties:
compatible:
oneOf:
- const: snps,dw-wdt
- items:
- enum:
- rockchip,px30-wdt
- rockchip,rk3066-wdt
- rockchip,rk3128-wdt
- rockchip,rk3188-wdt
- rockchip,rk3228-wdt
- rockchip,rk3288-wdt
- rockchip,rk3308-wdt
- rockchip,rk3328-wdt
- rockchip,rk3368-wdt
- rockchip,rk3399-wdt
- rockchip,rk3568-wdt
- rockchip,rv1108-wdt
- const: snps,dw-wdt
reg:
maxItems: 1
interrupts:
description: DW Watchdog pre-timeout interrupt
maxItems: 1
clocks:
minItems: 1
items:
- description: Watchdog timer reference clock
- description: APB3 interface clock
clock-names:
minItems: 1
items:
- const: tclk
- const: pclk
resets:
description: Phandle to the DW Watchdog reset lane
maxItems: 1
snps,watchdog-tops:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
DW APB Watchdog custom timer intervals - Timeout Period ranges (TOPs).
Each TOP is a number loaded into the watchdog counter at the moment of
the timer restart. The counter decrementing happens each tick of the
reference clock. Therefore the TOPs array is equivalent to an array of
the timer expiration intervals supported by the DW APB Watchdog. Note
DW APB Watchdog IP-core might be synthesized with fixed TOP values,
in which case this property is unnecessary with default TOPs utilized.
default: [0x0001000 0x0002000 0x0004000 0x0008000
0x0010000 0x0020000 0x0040000 0x0080000
0x0100000 0x0200000 0x0400000 0x0800000
0x1000000 0x2000000 0x4000000 0x8000000]
minItems: 16
maxItems: 16
unevaluatedProperties: false
required:
- compatible
- reg
- clocks
examples:
- |
watchdog@ffd02000 {
compatible = "snps,dw-wdt";
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&per_base_clk>;
resets = <&wdt_rst>;
};
- |
watchdog@ffd02000 {
compatible = "snps,dw-wdt";
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&per_base_clk>;
clock-names = "tclk";
snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
0x000007FF 0x0000FFFF 0x0001FFFF
0x0003FFFF 0x0007FFFF 0x000FFFFF
0x001FFFFF 0x003FFFFF 0x007FFFFF
0x00FFFFFF 0x01FFFFFF 0x03FFFFFF
0x07FFFFFF>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/socionext,uniphier-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier watchdog timer
maintainers:
- Keiji Hayashibara <hayashibara.keiji@socionext.com>
allOf:
- $ref: "watchdog.yaml#"
properties:
compatible:
const: socionext,uniphier-wdt
required:
- compatible
unevaluatedProperties: false
examples:
- |
// The UniPhier watchdog should be a subnode of a "syscon" compatible node.
sysctrl@61840000 {
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
watchdog {
compatible = "socionext,uniphier-wdt";
};
};

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Spreadtrum SoCs Watchdog timer
Required properties:
- compatible : Should be "sprd,sp9860-wdt".
- reg : Specifies base physical address and size of the registers.
- interrupts : Exactly one interrupt specifier.
- timeout-sec : Contain the default watchdog timeout in seconds.
- clock-names : Contain the input clock names.
- clocks : Phandles to input clocks.
Example:
watchdog: watchdog@40310000 {
compatible = "sprd,sp9860-wdt";
reg = <0 0x40310000 0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <12>;
clock-names = "enable", "rtc_enable";
clocks = <&clk_aon_apb_gates1 8>, <&clk_aon_apb_rtc_gates 9>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/st,stm32-iwdg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 Independent WatchDoG (IWDG) bindings
maintainers:
- Yannick Fertre <yannick.fertre@foss.st.com>
- Christophe Roullier <christophe.roullier@foss.st.com>
allOf:
- $ref: "watchdog.yaml#"
properties:
compatible:
enum:
- st,stm32-iwdg
- st,stm32mp1-iwdg
reg:
maxItems: 1
clocks:
items:
- description: Low speed clock
- description: Optional peripheral clock
minItems: 1
clock-names:
items:
enum:
- lsi
- pclk
minItems: 1
maxItems: 2
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
clock-names = "pclk", "lsi";
timeout-sec = <32>;
};
...

41
bindings/watchdog/st_lpc_wdt.txt Normal file
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STMicroelectronics Low Power Controller (LPC) - Watchdog
========================================================
LPC currently supports Watchdog OR Real Time Clock OR Clocksource
functionality.
[See: ../rtc/rtc-st-lpc.txt for RTC options]
[See: ../timer/st,stih407-lpc for Clocksource options]
Required properties
- compatible : Should be: "st,stih407-lpc"
- reg : LPC registers base address + size
- interrupts : LPC interrupt line number and associated flags
- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
- st,lpc-mode : The LPC can run either one of three modes:
ST_LPC_MODE_RTC [0]
ST_LPC_MODE_WDT [1]
ST_LPC_MODE_CLKSRC [2]
One (and only one) mode must be selected.
Required properties [watchdog mode]
- st,syscfg : Phandle to syscfg node used to enable watchdog and configure
CPU reset type.
- timeout-sec : Watchdog timeout in seconds
Optional properties [watchdog mode]
- st,warm-reset : If present reset type will be 'warm' - if not it will be cold
Example:
lpc@fde05000 {
compatible = "st,stih407-lpc";
reg = <0xfde05000 0x1000>;
clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
st,syscfg = <&syscfg_core>;
timeout-sec = <120>;
st,lpc-mode = <ST_LPC_MODE_WDT>;
st,warm-reset;
};

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bindings/watchdog/sunplus,sp7021-wdt.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/sunplus,sp7021-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sunplus SoCs Watchdog
maintainers:
- XianTao Hu <xt.hu@cqplus1.com>
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
const: sunplus,sp7021-wdt
reg:
items:
- description: watchdog registers regions
- description: miscellaneous control registers regions
clocks:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
- clocks
- resets
additionalProperties: false
examples:
- |
watchdog: watchdog@9c000630 {
compatible = "sunplus,sp7021-wdt";
reg = <0x9c000630 0x08>, <0x9c000274 0x04>;
clocks = <&clkc 0x24>;
resets = <&rstc 0x14>;
};
...

61
bindings/watchdog/ti,rti-wdt.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/ti,rti-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments K3 SoC Watchdog Timer
maintainers:
- Tero Kristo <t-kristo@ti.com>
description:
The TI K3 SoC watchdog timer is implemented via the RTI (Real Time
Interrupt) IP module. This timer adds a support for windowed watchdog
mode, which will signal an error if it is pinged outside the watchdog
time window, meaning either too early or too late. The error signal
generated can be routed to either interrupt a safety controller or
to directly reset the SoC.
allOf:
- $ref: "watchdog.yaml#"
properties:
compatible:
enum:
- ti,j7-rti-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- clocks
- power-domains
unevaluatedProperties: false
examples:
- |
/*
* RTI WDT in main domain on J721e SoC. Assigned clocks are used to
* select the source clock for the watchdog, forcing it to tick with
* a 32kHz clock in this case.
*/
#include <dt-bindings/soc/ti,sci_pm_domain.h>
watchdog@2200000 {
compatible = "ti,j7-rti-wdt";
reg = <0x2200000 0x100>;
clocks = <&k3_clks 252 1>;
power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 252 1>;
assigned-clock-parents = <&k3_clks 252 5>;
};

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bindings/watchdog/toshiba,visconti-wdt.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 Toshiba Electronic Devices & Storage Corporation
%YAML 1.2
---
$id: "http://devicetree.org/schemas/watchdog/toshiba,visconti-wdt.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Toshiba Visconti SoCs PIUWDT Watchdog timer
maintainers:
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
enum:
- toshiba,visconti-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
timeout-sec: true
required:
- compatible
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/toshiba,tmpv770x.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
wdt: watchdog@28330000 {
compatible = "toshiba,visconti-wdt";
reg = <0 0x28330000 0 0x1000>;
timeout-sec = <20>;
clocks = <&pismu TMPV770X_CLK_WDTCLK>;
};
};

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bindings/watchdog/ts4800-wdt.txt Normal file
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Technologic Systems Watchdog
Required properties:
- compatible: must be "technologic,ts4800-wdt"
- syscon: phandle / integer array that points to the syscon node which
describes the FPGA's syscon registers.
- phandle to FPGA's syscon
- offset to the watchdog register
Optional property:
- timeout-sec: contains the watchdog timeout in seconds.
Example:
syscon: syscon@b0010000 {
compatible = "syscon", "simple-mfd";
reg = <0xb0010000 0x3d>;
reg-io-width = <2>;
wdt@e {
compatible = "technologic,ts4800-wdt";
syscon = <&syscon 0xe>;
timeout-sec = <10>;
};
}

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bindings/watchdog/twl4030-wdt.txt Normal file
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Device tree bindings for twl4030-wdt driver (TWL4030 watchdog)
Required properties:
compatible = "ti,twl4030-wdt";
Example:
watchdog {
compatible = "ti,twl4030-wdt";
};

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bindings/watchdog/watchdog.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/watchdog.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Watchdog Generic Bindings
maintainers:
- Guenter Roeck <linux@roeck-us.net>
- Wim Van Sebroeck <wim@linux-watchdog.org>
description: |
This document describes generic bindings which can be used to
describe watchdog devices in a device tree.
properties:
$nodename:
pattern: "^watchdog(@.*|-[0-9a-f])?$"
timeout-sec:
description:
Contains the watchdog timeout in seconds.
additionalProperties: true
...

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bindings/watchdog/xlnx,xps-timebase-wdt.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx AXI/PLB softcore and window Watchdog Timer
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
- Srinivas Neeli <srinivas.neeli@xilinx.com>
description:
The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
WDT uses a dual-expiration architecture. After one expiration of
the timeout interval, an interrupt is generated and the WDT state
bit is set to one in the status register. If the state bit is not
cleared (by writing a one to the state bit) before the next
expiration of the timeout interval, a WDT reset is generated.
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
enum:
- xlnx,xps-timebase-wdt-1.01.a
- xlnx,xps-timebase-wdt-1.00.a
reg:
maxItems: 1
clocks:
maxItems: 1
clock-frequency:
description: Frequency of clock in Hz
xlnx,wdt-interval:
$ref: /schemas/types.yaml#/definitions/uint32
description: Watchdog timeout interval
minimum: 8
maximum: 32
xlnx,wdt-enable-once:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: If watchdog is configured as enable once,
then the watchdog cannot be disabled after
it has been enabled.
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
watchdog@40100000 {
compatible = "xlnx,xps-timebase-wdt-1.00.a";
reg = <0x40100000 0x1000>;
clock-frequency = <50000000>;
clocks = <&clkc 15>;
xlnx,wdt-enable-once = <0x0>;
xlnx,wdt-interval = <0x1b>;
};
...

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bindings/watchdog/zii,rave-sp-wdt.txt Normal file
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Zodiac Inflight Innovations RAVE Supervisory Processor Watchdog Bindings
RAVE SP watchdog device is a "MFD cell" device corresponding to
watchdog functionality of RAVE Supervisory Processor. It is expected
that its Device Tree node is specified as a child of the node
corresponding to the parent RAVE SP device (as documented in
Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
Required properties:
- compatible: Depending on wire protocol implemented by RAVE SP
firmware, should be one of:
- "zii,rave-sp-watchdog"
- "zii,rave-sp-watchdog-legacy"
Optional properties:
- wdt-timeout: Two byte nvmem cell specified as per
Documentation/devicetree/bindings/nvmem/nvmem.txt
Example:
rave-sp {
compatible = "zii,rave-sp-rdu1";
current-speed = <38400>;
eeprom {
wdt_timeout: wdt-timeout@8E {
reg = <0x8E 2>;
};
};
watchdog {
compatible = "zii,rave-sp-watchdog";
nvmem-cells = <&wdt_timeout>;
nvmem-cell-names = "wdt-timeout";
};
}

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bindings/watchdog/ziirave-wdt.txt Normal file
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Zodiac RAVE Watchdog Timer
Required properties:
- compatible: must be "zii,rave-wdt"
- reg: i2c slave address of device, usually 0x38
Optional Properties:
- timeout-sec: Watchdog timeout value in seconds.
- reset-duration-ms: Duration of the pulse generated when the watchdog times
out. Value in milliseconds.
Example:
watchdog@38 {
compatible = "zii,rave-wdt";
reg = <0x38>;
timeout-sec = <30>;
reset-duration-ms = <30>;
};