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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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71
bindings/ufs/cdns,ufshc.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence Universal Flash Storage (UFS) Controller
maintainers:
- Jan Kotas <jank@cadence.com>
# Select only our matches, not all jedec,ufs-2.0
select:
properties:
compatible:
contains:
enum:
- cdns,ufshc
- cdns,ufshc-m31-16nm
required:
- compatible
allOf:
- $ref: ufs-common.yaml
properties:
compatible:
items:
- enum:
- cdns,ufshc
# CDNS UFS HC + M31 16nm PHY
- cdns,ufshc-m31-16nm
- const: jedec,ufs-2.0
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
items:
- const: core_clk
- const: phy_clk
- const: ref_clk
power-domains:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
ufs@fd030000 {
compatible = "cdns,ufshc", "jedec,ufs-2.0";
reg = <0xfd030000 0x10000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
freq-table-hz = <0 0>, <0 0>;
clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
clock-names = "core_clk", "phy_clk";
};

90
bindings/ufs/hisilicon,ufs.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/hisilicon,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HiSilicon Universal Flash Storage (UFS) Controller
maintainers:
- Li Wei <liwei213@huawei.com>
# Select only our matches, not all jedec,ufs
select:
properties:
compatible:
contains:
enum:
- hisilicon,hi3660-ufs
- hisilicon,hi3670-ufs
required:
- compatible
allOf:
- $ref: ufs-common.yaml
properties:
compatible:
oneOf:
- items:
- const: hisilicon,hi3660-ufs
- const: jedec,ufs-1.1
- items:
- enum:
- hisilicon,hi3670-ufs
- const: jedec,ufs-2.1
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: ref_clk
- const: phy_clk
reg:
items:
- description: UFS register address space
- description: UFS SYS CTRL register address space
resets:
maxItems: 1
reset-names:
items:
- const: rst
required:
- compatible
- reg
- resets
- reset-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/hi3670-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
ufs@ff3c0000 {
compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
reg = <0x0 0xff3c0000 0x0 0x1000>,
<0x0 0xff3e0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
clock-names = "ref_clk", "phy_clk";
freq-table-hz = <0 0>,
<0 0>;
resets = <&crg_rst 0x84 12>;
reset-names = "rst";
};
};

67
bindings/ufs/mediatek,ufs.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Universal Flash Storage (UFS) Controller
maintainers:
- Stanley Chu <stanley.chu@mediatek.com>
allOf:
- $ref: ufs-common.yaml
properties:
compatible:
enum:
- mediatek,mt8183-ufshci
- mediatek,mt8192-ufshci
clocks:
maxItems: 1
clock-names:
items:
- const: ufs
phys:
maxItems: 1
reg:
maxItems: 1
vcc-supply: true
required:
- compatible
- clocks
- clock-names
- phys
- reg
- vcc-supply
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
ufs@ff3c0000 {
compatible = "mediatek,mt8183-ufshci";
reg = <0 0x11270000 0 0x2300>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
phys = <&ufsphy>;
clocks = <&infracfg_ao CLK_INFRA_UFS>;
clock-names = "ufs";
freq-table-hz = <0 0>;
vcc-supply = <&mt_pmic_vemc_ldo_reg>;
};
};

246
bindings/ufs/qcom,ufs.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Universal Flash Storage (UFS) Controller
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Andy Gross <agross@kernel.org>
# Select only our matches, not all jedec,ufs-2.0
select:
properties:
compatible:
contains:
const: qcom,ufshc
required:
- compatible
properties:
compatible:
items:
- enum:
- qcom,msm8994-ufshc
- qcom,msm8996-ufshc
- qcom,msm8998-ufshc
- qcom,sc8280xp-ufshc
- qcom,sdm845-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- qcom,sm8450-ufshc
- const: qcom,ufshc
- const: jedec,ufs-2.0
clocks:
minItems: 8
maxItems: 11
clock-names:
minItems: 8
maxItems: 11
interconnects:
minItems: 2
maxItems: 2
interconnect-names:
items:
- const: ufs-ddr
- const: cpu-ufs
iommus:
minItems: 1
maxItems: 2
phys:
maxItems: 1
phy-names:
items:
- const: ufsphy
power-domains:
maxItems: 1
reg:
minItems: 1
maxItems: 2
resets:
maxItems: 1
'#reset-cells':
const: 1
reset-names:
items:
- const: rst
reset-gpios:
maxItems: 1
description:
GPIO connected to the RESET pin of the UFS memory device.
required:
- compatible
- reg
allOf:
- $ref: ufs-common.yaml
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8998-ufshc
- qcom,sc8280xp-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- qcom,sm8450-ufshc
then:
properties:
clocks:
minItems: 8
maxItems: 8
clock-names:
items:
- const: core_clk
- const: bus_aggr_clk
- const: iface_clk
- const: core_clk_unipro
- const: ref_clk
- const: tx_lane0_sync_clk
- const: rx_lane0_sync_clk
- const: rx_lane1_sync_clk
reg:
minItems: 1
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm845-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
then:
properties:
clocks:
minItems: 9
maxItems: 9
clock-names:
items:
- const: core_clk
- const: bus_aggr_clk
- const: iface_clk
- const: core_clk_unipro
- const: ref_clk
- const: tx_lane0_sync_clk
- const: rx_lane0_sync_clk
- const: rx_lane1_sync_clk
- const: ice_core_clk
reg:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-ufshc
then:
properties:
clocks:
minItems: 11
maxItems: 11
clock-names:
items:
- const: core_clk_src
- const: core_clk
- const: bus_clk
- const: bus_aggr_clk
- const: iface_clk
- const: core_clk_unipro_src
- const: core_clk_unipro
- const: core_clk_ice
- const: ref_clk
- const: tx_lane0_sync_clk
- const: rx_lane0_sync_clk
reg:
minItems: 1
maxItems: 1
# TODO: define clock bindings for qcom,msm8994-ufshc
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
ufs@1d84000 {
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l7b_2p5>;
vcc-max-microamp = <1100000>;
vccq-supply = <&vreg_l9b_1p2>;
vccq-max-microamp = <1200000>;
power-domains = <&gcc UFS_PHY_GDSC>;
iommus = <&apps_smmu 0xe0 0x0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz = <75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>;
};
};

61
bindings/ufs/renesas,ufs.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/renesas,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car UFS Host Controller
maintainers:
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
allOf:
- $ref: ufs-common.yaml
properties:
compatible:
const: renesas,r8a779f0-ufs
reg:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: fck
- const: ref_clk
power-domains:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
- resets
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a779f0-sysc.h>
ufs: ufs@e686000 {
compatible = "renesas,r8a779f0-ufs";
reg = <0xe6860000 0x100>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
clock-names = "fck", "ref_clk";
freq-table-hz = <200000000 200000000>, <38400000 38400000>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 1514>;
};

95
bindings/ufs/samsung,exynos-ufs.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung SoC series UFS host controller
maintainers:
- Alim Akhtar <alim.akhtar@samsung.com>
description: |
Each Samsung UFS host controller instance should have its own node.
allOf:
- $ref: ufs-common.yaml
properties:
compatible:
enum:
- samsung,exynos7-ufs
- samsung,exynosautov9-ufs
- samsung,exynosautov9-ufs-vh
- tesla,fsd-ufs
reg:
items:
- description: HCI register
- description: vendor specific register
- description: unipro register
- description: UFS protector register
reg-names:
items:
- const: hci
- const: vs_hci
- const: unipro
- const: ufsp
clocks:
items:
- description: ufs link core clock
- description: unipro main clock
clock-names:
items:
- const: core_clk
- const: sclk_unipro_main
phys:
maxItems: 1
phy-names:
const: ufs-phy
samsung,sysreg:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
description: Should be phandle/offset pair. The phandle to the syscon node
which indicates the FSYSx sysreg interface and the offset of
the control register for UFS io coherency setting.
dma-coherent: true
required:
- compatible
- reg
- phys
- phy-names
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/exynos7-clk.h>
ufs: ufs@15570000 {
compatible = "samsung,exynos7-ufs";
reg = <0x15570000 0x100>,
<0x15570100 0x100>,
<0x15571000 0x200>,
<0x15572000 0x300>;
reg-names = "hci", "vs_hci", "unipro", "ufsp";
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
<&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
clock-names = "core_clk", "sclk_unipro_main";
pinctrl-names = "default";
pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
phys = <&ufs_phy>;
phy-names = "ufs-phy";
};
...

51
bindings/ufs/snps,tc-dwc-g210.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DesignWare Universal Flash Storage (UFS) Controller
maintainers:
- Li Wei <liwei213@huawei.com>
# Select only our matches, not all jedec,ufs
select:
properties:
compatible:
contains:
enum:
- snps,dwc-ufshcd-1.40a
required:
- compatible
allOf:
- $ref: ufs-common.yaml
properties:
compatible:
items:
- enum:
- snps,g210-tc-6.00-20bit
- snps,g210-tc-6.00-40bit
- const: snps,dwc-ufshcd-1.40a
- const: jedec,ufs-2.0
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
ufs@d0000000 {
compatible = "snps,g210-tc-6.00-40bit",
"snps,dwc-ufshcd-1.40a",
"jedec,ufs-2.0";
reg = <0xd0000000 0x10000>;
interrupts = <24>;
};

90
bindings/ufs/ti,j721e-ufs.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI J721e UFS Host Controller Glue Driver
maintainers:
- Vignesh Raghavendra <vigneshr@ti.com>
properties:
compatible:
items:
- const: ti,j721e-ufs
reg:
maxItems: 1
description: address of TI UFS glue registers
clocks:
maxItems: 1
description: phandle to the M-PHY clock
power-domains:
maxItems: 1
assigned-clocks:
maxItems: 1
assigned-clock-parents:
maxItems: 1
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
required:
- compatible
- reg
- clocks
- power-domains
patternProperties:
"^ufs@[0-9a-f]+$":
$ref: cdns,ufshc.yaml
description: |
Cadence UFS controller node must be the child node.
unevaluatedProperties: false
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
ufs-wrapper@4e80000 {
compatible = "ti,j721e-ufs";
reg = <0x0 0x4e80000 0x0 0x100>;
power-domains = <&k3_pds 277>;
clocks = <&k3_clks 277 1>;
assigned-clocks = <&k3_clks 277 1>;
assigned-clock-parents = <&k3_clks 277 4>;
ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
#address-cells = <2>;
#size-cells = <2>;
ufs@4000 {
compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
reg = <0x0 0x4000 0x0 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
freq-table-hz = <19200000 19200000>;
power-domains = <&k3_pds 277>;
clocks = <&k3_clks 277 1>;
assigned-clocks = <&k3_clks 277 1>;
assigned-clock-parents = <&k3_clks 277 4>;
clock-names = "core_clk";
};
};
};

82
bindings/ufs/ufs-common.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common properties for Universal Flash Storage (UFS) Host Controllers
maintainers:
- Alim Akhtar <alim.akhtar@samsung.com>
- Avri Altman <avri.altman@wdc.com>
properties:
clocks: true
clock-names: true
freq-table-hz:
items:
items:
- description: Minimum frequency for given clock in Hz
- description: Maximum frequency for given clock in Hz
description: |
Array of <min max> operating frequencies in Hz stored in the same order
as the clocks property. If this property is not defined or a value in the
array is "0" then it is assumed that the frequency is set by the parent
clock or a fixed rate clock source.
interrupts:
maxItems: 1
lanes-per-direction:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2]
default: 2
description:
Number of lanes available per direction. Note that it is assume same
number of lanes is used both directions at once.
vdd-hba-supply:
description:
Phandle to UFS host controller supply regulator node.
vcc-supply:
description:
Phandle to VCC supply regulator node.
vccq-supply:
description:
Phandle to VCCQ supply regulator node.
vccq2-supply:
description:
Phandle to VCCQ2 supply regulator node.
vcc-supply-1p8:
type: boolean
description:
For embedded UFS devices, valid VCC range is 1.7-1.95V or 2.7-3.6V. This
boolean property when set, specifies to use low voltage range of
1.7-1.95V. Note for external UFS cards this property is invalid and valid
VCC range is always 2.7-3.6V.
vcc-max-microamp:
description:
Specifies max. load that can be drawn from VCC supply.
vccq-max-microamp:
description:
Specifies max. load that can be drawn from VCCQ supply.
vccq2-max-microamp:
description:
Specifies max. load that can be drawn from VCCQ2 supply.
dependencies:
freq-table-hz: [ 'clocks' ]
required:
- interrupts
additionalProperties: true