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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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132
bindings/sram/allwinner,sun4i-a10-system-control.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 System Control
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
description:
The SRAM controller found on most Allwinner devices is represented
by a regular node for the SRAM controller itself, with sub-nodes
representing the SRAM handled by the SRAM controller.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 1
compatible:
oneOf:
- enum:
- allwinner,sun4i-a10-sram-controller
- allwinner,sun50i-a64-sram-controller
deprecated: true
- enum:
- allwinner,sun4i-a10-system-control
- allwinner,sun5i-a13-system-control
- allwinner,sun8i-a23-system-control
- allwinner,sun8i-h3-system-control
- allwinner,sun20i-d1-system-control
- allwinner,sun50i-a64-system-control
- allwinner,sun50i-h5-system-control
- allwinner,sun50i-h616-system-control
- items:
- enum:
- allwinner,suniv-f1c100s-system-control
- allwinner,sun7i-a20-system-control
- allwinner,sun8i-r40-system-control
- const: allwinner,sun4i-a10-system-control
- items:
- const: allwinner,sun8i-v3s-system-control
- const: allwinner,sun8i-h3-system-control
- items:
- const: allwinner,sun50i-h6-system-control
- const: allwinner,sun50i-a64-system-control
reg:
maxItems: 1
ranges: true
patternProperties:
"^sram@[a-z0-9]+":
type: object
properties:
compatible:
const: mmio-sram
patternProperties:
"^sram-section?@[a-f0-9]+$":
type: object
properties:
compatible:
oneOf:
- const: allwinner,sun4i-a10-sram-a3-a4
- const: allwinner,sun4i-a10-sram-c1
- const: allwinner,sun4i-a10-sram-d
- const: allwinner,sun50i-a64-sram-c
- items:
- enum:
- allwinner,sun5i-a13-sram-a3-a4
- allwinner,sun7i-a20-sram-a3-a4
- const: allwinner,sun4i-a10-sram-a3-a4
- items:
- enum:
- allwinner,sun5i-a13-sram-c1
- allwinner,sun7i-a20-sram-c1
- allwinner,sun8i-a23-sram-c1
- allwinner,sun8i-h3-sram-c1
- allwinner,sun8i-r40-sram-c1
- allwinner,sun50i-a64-sram-c1
- allwinner,sun50i-h5-sram-c1
- allwinner,sun50i-h6-sram-c1
- const: allwinner,sun4i-a10-sram-c1
- items:
- enum:
- allwinner,suniv-f1c100s-sram-d
- allwinner,sun5i-a13-sram-d
- allwinner,sun7i-a20-sram-d
- const: allwinner,sun4i-a10-sram-d
- items:
- const: allwinner,sun50i-h6-sram-c
- const: allwinner,sun50i-a64-sram-c
required:
- "#address-cells"
- "#size-cells"
- compatible
- reg
additionalProperties: false
examples:
- |
system-control@1c00000 {
compatible = "allwinner,sun4i-a10-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_a: sram@0 {
compatible = "mmio-sram";
reg = <0x00000000 0xc000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00000000 0xc000>;
emac_sram: sram-section@8000 {
compatible = "allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
};
};
};

76
bindings/sram/qcom,imem.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/sram/qcom,imem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm IMEM memory region
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
Qualcomm IMEM is dedicated memory region for various debug features and DMA
transactions.
properties:
compatible:
items:
- enum:
- qcom,apq8064-imem
- qcom,msm8974-imem
- qcom,qcs404-imem
- qcom,sc7180-imem
- qcom,sc7280-imem
- qcom,sdm630-imem
- qcom,sdm845-imem
- qcom,sdx55-imem
- qcom,sdx65-imem
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
ranges: true
'#address-cells':
const: 1
'#size-cells':
const: 1
reboot-mode:
$ref: /schemas/power/reset/syscon-reboot-mode.yaml#
patternProperties:
"^pil-reloc@[0-9a-f]+$":
$ref: /schemas/remoteproc/qcom,pil-info.yaml#
description: Peripheral image loader relocation region
required:
- compatible
- reg
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
sram@146bf000 {
compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
reg = <0 0x146bf000 0 0x1000>;
ranges = <0 0 0x146bf000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
pil-reloc@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
};
};

98
bindings/sram/qcom,ocmem.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sram/qcom,ocmem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: On Chip Memory (OCMEM) that is present on some Qualcomm Snapdragon SoCs.
maintainers:
- Brian Masney <masneyb@onstation.org>
description: |
The On Chip Memory (OCMEM) is typically used by the GPU, camera/video, and
audio components on some Snapdragon SoCs.
properties:
compatible:
const: qcom,msm8974-ocmem
reg:
items:
- description: Control registers
- description: OCMEM address range
reg-names:
items:
- const: ctrl
- const: mem
clocks:
items:
- description: Core clock
- description: Interface clock
clock-names:
items:
- const: core
- const: iface
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges:
maxItems: 1
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- '#address-cells'
- '#size-cells'
- ranges
additionalProperties: false
patternProperties:
"-sram@[0-9a-f]+$":
type: object
description: A region of reserved memory.
properties:
reg:
maxItems: 1
required:
- reg
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
sram@fdd00000 {
compatible = "qcom,msm8974-ocmem";
reg = <0xfdd00000 0x2000>,
<0xfec00000 0x180000>;
reg-names = "ctrl",
"mem";
clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
<&mmcc OCMEMCX_OCMEMNOC_CLK>;
clock-names = "core",
"iface";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfec00000 0x100000>;
gmu-sram@0 {
reg = <0x0 0x100000>;
};
};

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bindings/sram/sram.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/sram/sram.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic on-chip SRAM
maintainers:
- Rob Herring <robh@kernel.org>
description: |+
Simple IO memory regions to be managed by the genalloc API.
Each child of the sram node specifies a region of reserved memory. Each
child node should use a 'reg' property to specify a specific range of
reserved memory.
Following the generic-names recommended practice, node names should
reflect the purpose of the node. Unit address (@<address>) should be
appended to the name.
properties:
$nodename:
pattern: "^sram(@.*)?"
compatible:
contains:
enum:
- mmio-sram
- amlogic,meson-gxbb-sram
- arm,juno-sram-ns
- atmel,sama5d2-securam
- nvidia,tegra186-sysram
- nvidia,tegra194-sysram
- nvidia,tegra234-sysram
- qcom,rpm-msg-ram
- rockchip,rk3288-pmu-sram
reg:
maxItems: 1
clocks:
maxItems: 1
description:
A list of phandle and clock specifier pair that controls the single
SRAM clock.
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges:
maxItems: 1
description:
Should translate from local addresses within the sram to bus addresses.
no-memory-wc:
description:
The flag indicating, that SRAM memory region has not to be remapped
as write combining. WC is used by default.
type: boolean
patternProperties:
"^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$":
type: object
description:
Each child of the sram node specifies a region of reserved memory.
properties:
compatible:
description:
Should contain a vendor specific string in the form
<vendor>,[<device>-]<usage>
contains:
enum:
- allwinner,sun4i-a10-sram-a3-a4
- allwinner,sun4i-a10-sram-c1
- allwinner,sun4i-a10-sram-d
- allwinner,sun9i-a80-smp-sram
- allwinner,sun50i-a64-sram-c
- amlogic,meson8-ao-arc-sram
- amlogic,meson8b-ao-arc-sram
- amlogic,meson8-smp-sram
- amlogic,meson8b-smp-sram
- amlogic,meson-gxbb-scp-shmem
- amlogic,meson-axg-scp-shmem
- arm,juno-scp-shmem
- arm,scmi-shmem
- arm,scp-shmem
- renesas,smp-sram
- rockchip,rk3066-smp-sram
- samsung,exynos4210-sysram
- samsung,exynos4210-sysram-ns
- socionext,milbeaut-smp-sram
reg:
description:
IO mem address range, relative to the SRAM range.
maxItems: 1
pool:
description:
Indicates that the particular reserved SRAM area is addressable
and in use by another device or devices.
type: boolean
export:
description:
Indicates that the reserved SRAM area may be accessed outside
of the kernel, e.g. by bootloader or userspace.
type: boolean
protect-exec:
description: |
Same as 'pool' above but with the additional constraint that code
will be run from the region and that the memory is maintained as
read-only, executable during code execution. NOTE: This region must
be page aligned on start and end in order to properly allow
manipulation of the page attributes.
type: boolean
label:
description:
The name for the reserved partition, if omitted, the label is taken
from the node name excluding the unit address.
required:
- reg
additionalProperties: false
required:
- compatible
- reg
if:
not:
properties:
compatible:
contains:
enum:
- qcom,rpm-msg-ram
- rockchip,rk3288-pmu-sram
then:
required:
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
sram@5c000000 {
compatible = "mmio-sram";
reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5c000000 0x40000>;
smp-sram@100 {
reg = <0x100 0x50>;
};
device-sram@1000 {
reg = <0x1000 0x1000>;
pool;
};
exported-sram@20000 {
reg = <0x20000 0x20000>;
export;
};
};
- |
// Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
// of the secondary cores. Once the core gets powered up it executes the
// code that is residing at some specific location of the SYSRAM.
//
// Therefore reserved section sub-nodes have to be added to the mmio-sram
// declaration. These nodes are of two types depending upon secure or
// non-secure execution environment.
sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x54000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x54000>;
smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
smp-sram@53000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x53000 0x1000>;
};
};
- |
// Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
// Once the core gets powered up it executes the code that is residing at a
// specific location.
//
// Therefore a reserved section sub-node has to be added to the mmio-sram
// declaration.
sram@d9000000 {
compatible = "mmio-sram";
reg = <0xd9000000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xd9000000 0x20000>;
smp-sram@1ff80 {
compatible = "amlogic,meson8b-smp-sram";
reg = <0x1ff80 0x8>;
};
};
- |
sram@e63c0000 {
compatible = "mmio-sram";
reg = <0xe63c0000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
- |
sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
smp-sram@10080000 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x10080000 0x50>;
};
};
- |
// Rockchip's rk3288 SoC uses the sram of pmu to store the function of
// resume from maskrom(the 1st level loader). This is a common use of
// the "pmu-sram" because it keeps power even in low power states
// in the system.
sram@ff720000 {
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
reg = <0xff720000 0x1000>;
};
- |
// Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
// primary core (cpu0). Once the core gets powered up it checks if a magic
// value is set at a specific location. If it is then the BROM will jump
// to the software entry address, instead of executing a standard boot.
//
// Also there are no "secure-only" properties. The implementation should
// check if this SRAM is usable first.
sram@20000 {
// 256 KiB secure SRAM at 0x20000
compatible = "mmio-sram";
reg = <0x00020000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00020000 0x40000>;
smp-sram@1000 {
// This is checked by BROM to determine if
// cpu0 should jump to SMP entry vector
compatible = "allwinner,sun9i-a80-smp-sram";
reg = <0x1000 0x8>;
};
};
- |
sram@0 {
compatible = "mmio-sram";
reg = <0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x10000>;
smp-sram@f100 {
compatible = "socionext,milbeaut-smp-sram";
reg = <0xf100 0x20>;
};
};