dt-bindings: Add devicetree bindings
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
73
bindings/spmi/hisilicon,hisi-spmi-controller.yaml
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73
bindings/spmi/hisilicon,hisi-spmi-controller.yaml
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spmi/hisilicon,hisi-spmi-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: HiSilicon SPMI controller
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maintainers:
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- Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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description: |
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The HiSilicon SPMI BUS controller is found on some Kirin-based designs.
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It is a MIPI System Power Management (SPMI) controller.
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The PMIC part is provided by
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./Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml.
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allOf:
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- $ref: spmi.yaml#
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properties:
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$nodename:
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pattern: "spmi@[0-9a-f]"
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compatible:
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const: hisilicon,kirin970-spmi-controller
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reg:
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maxItems: 1
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hisilicon,spmi-channel:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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number of the Kirin 970 SPMI channel where the SPMI devices are connected.
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required:
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- compatible
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- reg
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- hisilicon,spmi-channel
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patternProperties:
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"@[0-9a-f]$":
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type: object
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description: |
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PMIC properties, which are specific to the used SPMI PMIC device(s).
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When used in combination with HiSilicon 6421v600, the properties
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are documented at
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drivers/staging/hikey9xx/hisilicon,hi6421-spmi-pmic.yaml.
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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spmi: spmi@fff24000 {
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compatible = "hisilicon,kirin970-spmi-controller";
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#address-cells = <2>;
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#size-cells = <0>;
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reg = <0x0 0xfff24000 0x0 0x1000>;
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hisilicon,spmi-channel = <2>;
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pmic@0 {
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reg = <0 0>;
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/* pmic properties */
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};
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};
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};
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76
bindings/spmi/mtk,spmi-mtk-pmif.yaml
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76
bindings/spmi/mtk,spmi-mtk-pmif.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek SPMI Controller
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maintainers:
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- Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
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description: |+
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On MediaTek SoCs the PMIC is connected via SPMI and the controller allows
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for multiple SoCs to control a single SPMI master.
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allOf:
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- $ref: "spmi.yaml"
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properties:
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compatible:
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enum:
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- mediatek,mt6873-spmi
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- mediatek,mt8195-spmi
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: pmif
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- const: spmimst
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: pmif_sys_ck
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- const: pmif_tmr_ck
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- const: spmimst_clk_mux
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assigned-clocks:
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maxItems: 1
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assigned-clock-parents:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8192-clk.h>
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spmi: spmi@10027000 {
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compatible = "mediatek,mt6873-spmi";
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reg = <0x10027000 0xe00>,
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<0x10029000 0x100>;
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reg-names = "pmif", "spmimst";
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clocks = <&infracfg CLK_INFRA_PMIC_AP>,
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<&infracfg CLK_INFRA_PMIC_TMR>,
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<&topckgen CLK_TOP_SPMI_MST_SEL>;
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clock-names = "pmif_sys_ck",
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"pmif_tmr_ck",
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"spmimst_clk_mux";
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assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
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};
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...
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117
bindings/spmi/qcom,spmi-pmic-arb.yaml
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117
bindings/spmi/qcom,spmi-pmic-arb.yaml
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SPMI Controller (PMIC Arbiter)
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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description: |
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The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
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controller with wrapping arbitration logic to allow for multiple on-chip
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devices to control a single SPMI master.
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The PMIC Arbiter can also act as an interrupt controller, providing interrupts
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to slave devices.
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allOf:
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- $ref: spmi.yaml
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properties:
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compatible:
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const: qcom,spmi-pmic-arb
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reg:
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oneOf:
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- items: # V1
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- description: core registers
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- description: interrupt controller registers
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- description: configuration registers
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- items: # V2
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- description: core registers
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- description: tx-channel per virtual slave regosters
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- description: rx-channel (called observer) per virtual slave registers
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- description: interrupt controller registers
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- description: configuration registers
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reg-names:
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oneOf:
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- items:
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- const: core
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- const: intr
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- const: cnfg
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- items:
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- const: core
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- const: chnls
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- const: obsrvr
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- const: intr
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- const: cnfg
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interrupts:
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maxItems: 1
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interrupt-names:
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const: periph_irq
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interrupt-controller: true
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'#address-cells': true
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'#interrupt-cells':
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const: 4
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description: |
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cell 1: slave ID for the requested interrupt (0-15)
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cell 2: peripheral ID for requested interrupt (0-255)
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cell 3: the requested peripheral interrupt (0-7)
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cell 4: interrupt flags indicating level-sense information,
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as defined in dt-bindings/interrupt-controller/irq.h
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'#size-cells': true
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qcom,ee:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 5
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description: >
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indicates the active Execution Environment identifier
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qcom,channel:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 5
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description: >
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which of the PMIC Arb provided channels to use for accesses
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required:
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- compatible
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- reg-names
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- qcom,ee
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- qcom,channel
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unevaluatedProperties: false
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examples:
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- |
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spmi@fc4cf000 {
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compatible = "qcom,spmi-pmic-arb";
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reg-names = "core", "intr", "cnfg";
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reg = <0xfc4cf000 0x1000>,
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<0xfc4cb000 0x1000>,
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<0xfc4ca000 0x1000>;
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interrupt-names = "periph_irq";
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interrupts = <0 190 0>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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};
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75
bindings/spmi/spmi.yaml
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75
bindings/spmi/spmi.yaml
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@@ -0,0 +1,75 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spmi/spmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: System Power Management Interface (SPMI) Controller
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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description: |
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The System Power Management (SPMI) controller is a 2-wire bus defined
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by the MIPI Alliance for power management control to be used on SoC designs.
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SPMI controllers are modelled in device tree using a generic set of
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bindings defined here, plus any bus controller specific properties, if
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needed.
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Each SPMI controller has zero or more child nodes (up to 16 ones), each
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one representing an unique slave at the bus.
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properties:
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$nodename:
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pattern: "^spmi@.*"
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"#address-cells":
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const: 2
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"#size-cells":
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const: 0
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patternProperties:
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"@[0-9a-f]$":
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description: up to 16 child PMIC nodes
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type: object
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properties:
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reg:
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items:
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- minItems: 1
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items:
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- minimum: 0
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maximum: 0xf
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- enum: [ 0 ]
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description:
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0 means user ID address. 1 is reserved for group ID
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address.
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required:
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- reg
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required:
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- reg
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additionalProperties: true
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examples:
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- |
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#include <dt-bindings/spmi/spmi.h>
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spmi@0 {
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reg = <0 0>;
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#address-cells = <2>;
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#size-cells = <0>;
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child@0 {
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reg = <0 SPMI_USID>;
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};
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child@7 {
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reg = <7 SPMI_USID>;
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};
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};
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